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Paper Abstract and Keywords
Presentation 2015-06-16 14:10
A test data reduction method based on scan slice on BAST
Makoto Nishikiori, Hiroshi Yamazaki, Toshinori Hosokawa, Masayuki Arai (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2015-16
Abstract (in Japanese) (See Japanese page) 
(in English) BAST is one of techniques to reduce the amount of test data while maintaining high test quality by combining built-in self test with deterministic test generation. On BAST architecture, a bit-flipping technique is used to convert pseudo-random patterns to deterministic patterns. The test data on BAST are consists of bit-flipping instructions and shift instructions. The number of bit-flipping instructions depends on that of conflicted bits between deterministic patterns and pseudo random patterns. Therefore, the number of conflicted bits must be reduced to decrease the amount of test data. In this paper, we focus that the number of the conflicted bits has variation at each scan slice. We propose a method to reduce the number of conflicted bits by applying an all bit-flipping instruction to scan slices with many conflicted bits. Experimental results show that the proposed method was effective to reduce the number of bit-flipping instructions and the amount of test data for ISCAS'89 and ITC'99 benchmark circuits.
Keyword (in Japanese) (See Japanese page) 
(in English) BAST architecture / scan slice / BAST code / bit-flipping instructions / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 86, DC2015-16, pp. 1-6, June 2015.
Paper # DC2015-16 
Date of Issue 2015-06-09 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2015-06-16 - 2015-06-16 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reliable design and Test, etc. 
Paper Information
Registration To DC 
Conference Code 2015-06-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A test data reduction method based on scan slice on BAST 
Sub Title (in English)  
Keyword(1) BAST architecture  
Keyword(2) scan slice  
Keyword(3) BAST code  
Keyword(4) bit-flipping instructions  
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1st Author's Name Makoto Nishikiori  
1st Author's Affiliation Nihon University (Nihon Univ.)
2nd Author's Name Hiroshi Yamazaki  
2nd Author's Affiliation Nihon University (Nihon Univ.)
3rd Author's Name Toshinori Hosokawa  
3rd Author's Affiliation Nihon University (Nihon Univ.)
4th Author's Name Masayuki Arai  
4th Author's Affiliation Nihon University (Nihon Univ.)
5th Author's Name Masayoshi Yoshimura  
5th Author's Affiliation Kyoto Sangyo University (Kyoto Sangyo Univ.)
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Speaker Author-1 
Date Time 2015-06-16 14:10:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2015-16 
Volume (vol) vol.115 
Number (no) no.86 
Page pp.1-6 
#Pages
Date of Issue 2015-06-09 (DC) 


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