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| Presentation | 2015-05-14 11:35 Control Signal Extraction for Sequential Clock Gating Using Time Expansion of Sequential Circuits Tomoya Goto, Kohei Higuchi, Masao Yanagisawa, Shinji Kimura (Waseda Univ.)  VLD2015-4 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Recently, clock gating is utilized as a method for reducing the dynamic power of LSI. Clock gating can be automatically inserted by the synthesis tools, but there are problems such as designers must specify control signals. So more aggressive and automatable clock gating techniques have been proposed. In this study, a clock gating candidate extraction method for combinational clock gating is enhanced to the method for sequential clock gating using time expansion of sequential circuits. Using time expansion and detection by SAT, it is possible to find multiple clock past signal as a candidate. The proposed method was applied to ISCAS'89 benchmark and we got more control signal candidates. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Clock Gating / Design Automation / Low power LSI design / Sequential Clock Gating / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 115, no. 21, VLD2015-4, pp. 31-36, May 2015. | |
| Paper # | VLD2015-4 | |
| Date of Issue | 2015-05-07 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2015-4 |
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| Conference Information | |
| Committee | VLD IPSJ-SLDM |
| Conference Date | 2015-05-14 - 2015-05-14 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kitakyushu International Conference Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System Design, etc. |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2015-05-VLD-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Control Signal Extraction for Sequential Clock Gating Using Time Expansion of Sequential Circuits |
| Sub Title (in English) | |
| Keyword(1) | Clock Gating |
| Keyword(2) | Design Automation |
| Keyword(3) | Low power LSI design |
| Keyword(4) | Sequential Clock Gating |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Tomoya Goto |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | Kohei Higuchi |
| 2nd Author's Affiliation | Waseda University (Waseda Univ.) |
| 3rd Author's Name | Masao Yanagisawa |
| 3rd Author's Affiliation | Waseda University (Waseda Univ.) |
| 4th Author's Name | Shinji Kimura |
| 4th Author's Affiliation | Waseda University (Waseda Univ.) |
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| Speaker | Author-1 |
| Date Time | 2015-05-14 11:35:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2015-4 |
| Volume (vol) | vol.115 |
| Number (no) | no.21 |
| Page | pp.31-36 |
| #Pages | 6 |
| Date of Issue | 2015-05-07 (VLD) |
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