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Paper Abstract and Keywords
Presentation 2015-04-17 14:55
[Invited Talk] An 1800-Times-Higher Power-Efficient 20k-spin Ising Chip for Combinatorial Optimization Problem with CMOS Annealing
Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno (Hitachi) ICD2015-13 Link to ES Tech. Rep. Archives: ICD2015-13
Abstract (in Japanese) (See Japanese page) 
(in English) A new computing architecture using Ising model that effectively solves combinatorial optimization problems is proposed, and a 20k-spin Ising chip is fabricated in 65nm process. The chip maps problems to an Ising model, a model to express the behavior of magnetic spins, and solves the problems by its own convergence property. The convergence is performed by CMOS circuits operations. The Ising chip achieves 100MHz operation and the operation to solve problems using Ising model is confirmed. The power efficiency of the chip is 1800-times higher than that of the conventional Neumann computers.
Keyword (in Japanese) (See Japanese page) 
(in English) Ising model / combinatorial optimization problem / SRAM / non-Neumann computer / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 6, ICD2015-13, pp. 63-68, April 2015.
Paper # ICD2015-13 
Date of Issue 2015-04-09 (ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2015-13 Link to ES Tech. Rep. Archives: ICD2015-13

Conference Information
Committee ICD  
Conference Date 2015-04-16 - 2015-04-17 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2015-04-ICD 
Language English (Japanese title is available) 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An 1800-Times-Higher Power-Efficient 20k-spin Ising Chip for Combinatorial Optimization Problem with CMOS Annealing 
Sub Title (in English)  
Keyword(1) Ising model  
Keyword(2) combinatorial optimization problem  
Keyword(3) SRAM  
Keyword(4) non-Neumann computer  
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1st Author's Name Masanao Yamaoka  
1st Author's Affiliation Hitachi, Ltd. (Hitachi)
2nd Author's Name Chihiro Yoshimura  
2nd Author's Affiliation Hitachi, Ltd. (Hitachi)
3rd Author's Name Masato Hayashi  
3rd Author's Affiliation Hitachi, Ltd. (Hitachi)
4th Author's Name Takuya Okuyama  
4th Author's Affiliation Hitachi, Ltd. (Hitachi)
5th Author's Name Hidetaka Aoki  
5th Author's Affiliation Hitachi, Ltd. (Hitachi)
6th Author's Name Hiroyuki Mizuno  
6th Author's Affiliation Hitachi, Ltd. (Hitachi)
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Speaker
Date Time 2015-04-17 14:55:00 
Presentation Time 50 
Registration for ICD 
Paper # IEICE-ICD2015-13 
Volume (vol) IEICE-115 
Number (no) no.6 
Page pp.63-68 
#Pages IEICE-6 
Date of Issue IEICE-ICD-2015-04-09 


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