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| Presentation | 2015-03-07 14:15 Speed Up co-Simulation for Verification of Embedded Systems Hiroaki Nakata, Kenta Morishima, Yasuo Sugure (Hitachi)  CPSY2014-183 DC2014-109 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In order to apply co-simulation method to verification of many embedded systems, we speeded up co-simulation between a microcomputer simulator and a plant simulator especially for the cases which require short-period synchronization between those simulators. By using dynamic linking method instead of interprocess communication, speed of simulation became up to 9.0 times faster in a case which kept synchronization every 10ns. Then a simulation of a brushless DC motor for 0.5 seconds in actual time was done in 6 minutes and some seconds. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Embedded Systems / Verification / Microcomputer Model / co-Simulation / Dynamic Linkage / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 507, DC2014-109, pp. 137-142, March 2015. | |
| Paper # | DC2014-109 | |
| Date of Issue | 2015-02-27 (CPSY, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2014-183 DC2014-109 |
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| Conference Information | |
| Committee | CPSY IPSJ-EMB IPSJ-SLDM DC |
| Conference Date | 2015-03-06 - 2015-03-07 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2015-03-CPSY-EMB-SLDM-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Speed Up co-Simulation for Verification of Embedded Systems |
| Sub Title (in English) | |
| Keyword(1) | Embedded Systems |
| Keyword(2) | Verification |
| Keyword(3) | Microcomputer Model |
| Keyword(4) | co-Simulation |
| Keyword(5) | Dynamic Linkage |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Hiroaki Nakata |
| 1st Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. (Hitachi) |
| 2nd Author's Name | Kenta Morishima |
| 2nd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. (Hitachi) |
| 3rd Author's Name | Yasuo Sugure |
| 3rd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. (Hitachi) |
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| Speaker | Author-1 |
| Date Time | 2015-03-07 14:15:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | CPSY2014-183, DC2014-109 |
| Volume (vol) | vol.114 |
| Number (no) | no.506(CPSY), no.507(DC) |
| Page | pp.137-142 |
| #Pages | 6 |
| Date of Issue | 2015-02-27 (CPSY, DC) |
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