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Paper Abstract and Keywords
Presentation 2015-03-07 09:20
A Study on a Power Efficient Neurochip with Non-Volatile Memory
Jun Tomii, Masaaki Kondo, Hiroshi Nakamura (Univ. Tokyo) CPSY2014-176 DC2014-102
Abstract (in Japanese) (See Japanese page) 
(in English) Along with the evolution of machine learning techniques, neurochips, which are designed for fast neural network processing, are getting important. Specially for large scale networks, reducing power consumption of neurochips is indispensable. In neurochips, leakage energy accounts for a large portion of total energy consumption. Therefore, in this paper, we study a neurochip with non-volatile memories to reduce leakage power of the neurochip. We develop a newrochip simulator and evaluate energy efficiency of the proposed neurochip compared with that with traditional SRAMs. From the evaluation results, we found out that non-volatile memory is effective for neurochips.
Keyword (in Japanese) (See Japanese page) 
(in English) Neurochip / Lower Power Consumption / Non-Volatile Memory / / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 506, CPSY2014-176, pp. 83-88, March 2015.
Paper # CPSY2014-176 
Date of Issue 2015-02-27 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee CPSY IPSJ-EMB IPSJ-SLDM DC  
Conference Date 2015-03-06 - 2015-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
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Paper Information
Registration To CPSY 
Conference Code 2015-03-CPSY-EMB-SLDM-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Study on a Power Efficient Neurochip with Non-Volatile Memory 
Sub Title (in English)  
Keyword(1) Neurochip  
Keyword(2) Lower Power Consumption  
Keyword(3) Non-Volatile Memory  
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1st Author's Name Jun Tomii  
1st Author's Affiliation The University of Tokyo (Univ. Tokyo)
2nd Author's Name Masaaki Kondo  
2nd Author's Affiliation The University of Tokyo (Univ. Tokyo)
3rd Author's Name Hiroshi Nakamura  
3rd Author's Affiliation The University of Tokyo (Univ. Tokyo)
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Speaker
Date Time 2015-03-07 09:20:00 
Presentation Time 25 
Registration for CPSY 
Paper # IEICE-CPSY2014-176,IEICE-DC2014-102 
Volume (vol) IEICE-114 
Number (no) no.506(CPSY), no.507(DC) 
Page pp.83-88 
#Pages IEICE-6 
Date of Issue IEICE-CPSY-2015-02-27,IEICE-DC-2015-02-27 


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