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| Presentation | 2015-03-06 16:05 A proposal of placement optimization algorithm by introducing TSV module Atsushi Murata, Tomohiro Inaba, Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga (UEC)  CPSY2014-169 DC2014-95 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The performance and the power efficiency of VLSI are expected to be significantly improved by the development of 3D stacking technologies. Various 3D floorplanner algorithms are proposed to optimize the design of future 3D-ICs,while they approximate the arrangement of TSVs, which diminishes the optimization. In this paper, novel algorithm that optimizes the location of TSVs as well as normal modules is proposed. Our algorithm is implemented and the optimization of 3d microprocessor floorplan is organized. The evaluation results show that there are some common tendency in effective TSV positions. It is also revealed that our algorithm estimates ``wire-activity'' cost function in 28.4％ higher accuracy for the optimization. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Three-dimensional stack technology / Floorplanner / TSV / Simulated Annealing / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 506, CPSY2014-169, pp. 43-48, March 2015. | |
| Paper # | CPSY2014-169 | |
| Date of Issue | 2015-02-27 (CPSY, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2014-169 DC2014-95 |
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| Conference Information | |
| Committee | CPSY IPSJ-EMB IPSJ-SLDM DC |
| Conference Date | 2015-03-06 - 2015-03-07 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2015-03-CPSY-EMB-SLDM-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A proposal of placement optimization algorithm by introducing TSV module |
| Sub Title (in English) | |
| Keyword(1) | Three-dimensional stack technology |
| Keyword(2) | Floorplanner |
| Keyword(3) | TSV |
| Keyword(4) | Simulated Annealing |
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| Keyword(8) | |
| 1st Author's Name | Atsushi Murata |
| 1st Author's Affiliation | The University of Electro Comunications (UEC) |
| 2nd Author's Name | Tomohiro Inaba |
| 2nd Author's Affiliation | The University of Electro Comunications (UEC) |
| 3rd Author's Name | Masato Yoshimi |
| 3rd Author's Affiliation | The University of Electro Comunications (UEC) |
| 4th Author's Name | Hidetsugu Irie |
| 4th Author's Affiliation | The University of Electro Comunications (UEC) |
| 5th Author's Name | Tsutomu Yoshinaga |
| 5th Author's Affiliation | The University of Electro Comunications (UEC) |
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| Speaker | Author-1 |
| Date Time | 2015-03-06 16:05:00 |
| Presentation Time | 25 minutes |
| Registration for | CPSY |
| Paper # | CPSY2014-169, DC2014-95 |
| Volume (vol) | vol.114 |
| Number (no) | no.506(CPSY), no.507(DC) |
| Page | pp.43-48 |
| #Pages | 6 |
| Date of Issue | 2015-02-27 (CPSY, DC) |
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