Paper Abstract and Keywords |
Presentation |
2015-03-04 10:20
Optimization of sequential circuit in gate-level pipelined self-synchronous circuit design Atsushi Ito, Makoto Ikeda (The Univ. of Tokyo) VLD2014-177 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
With the down-scaling, circuit which has higher robustness is demanded. Dual-pipeline self synchronous circuit have inherent robustness. However design flow for the circuit have not been automated. We investigated data flow in the loop circuit on self-synchronous circuits to clarify the constraint for sequential circuit on self-synchronous circuit. We proposed a method of optimization of sequential circuit in self-synchronous circuits design. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
gate-level pipeline / self synchronous / automated design / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 476, VLD2014-177, pp. 135-140, March 2015. |
Paper # |
VLD2014-177 |
Date of Issue |
2015-02-23 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2014-177 |
Conference Information |
Committee |
VLD |
Conference Date |
2015-03-02 - 2015-03-04 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawa Seinen Kaikan |
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(See Japanese page) |
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Paper Information |
Registration To |
VLD |
Conference Code |
2015-03-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Optimization of sequential circuit in gate-level pipelined self-synchronous circuit design |
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gate-level pipeline |
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self synchronous |
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automated design |
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1st Author's Name |
Atsushi Ito |
1st Author's Affiliation |
The University of Tokyo (The Univ. of Tokyo) |
2nd Author's Name |
Makoto Ikeda |
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The University of Tokyo (The Univ. of Tokyo) |
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Speaker |
Author-1 |
Date Time |
2015-03-04 10:20:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2014-177 |
Volume (vol) |
vol.114 |
Number (no) |
no.476 |
Page |
pp.135-140 |
#Pages |
6 |
Date of Issue |
2015-02-23 (VLD) |