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Paper Abstract and Keywords
Presentation 2015-03-03 16:15
[Memorial Lecture] A Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-173
Abstract (in Japanese) (See Japanese page) 
(in English) Non-volatile memory is superior to SRAM in terms of its high density and low leakage power
but it consumes larger writing energy than SRAM.
It is necessary to reduce writing energy to solve the problem.
In this paper, we reduce writing energy of non-volatile memory by decreasing the number of writing bits.
We propose a new code based on error-correcting codes and a bit-write reduction method using the code for non-volatile memory.
We call this new code a write-reduction code.
Our method uses encoder and decoder circuits around a memory architecture.
When writing a data, it is encoded into a write-reduction codeword and written into a memory cell.
When reading a data, a write-reduction codeword is decoded into a normal data.
In our write-reduction codes, each data corresponds to an information vector in an error-correcting code and an
information vector corresponds not to a single codeword but a set of write-reduction codewords.
When we encode a data to a codeword, the codeword minimizing the number of flipped bits is selected.
We demonstrate up to 75% writing bits reduction and up to 72% energy reduction.
Keyword (in Japanese) (See Japanese page) 
(in English) non-volatile memory / bit-write reduction / energy reduction / write-reduction code / error-correctin code / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 476, VLD2014-173, pp. 115-115, March 2015.
Paper # VLD2014-173 
Date of Issue 2015-02-23 (VLD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
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技術研究報告に掲載された論文の著作権はIEICEに帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-173

Conference Information
Committee VLD  
Conference Date 2015-03-02 - 2015-03-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2015-03-VLD 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories 
Sub Title (in English)  
Keyword(1) non-volatile memory  
Keyword(2) bit-write reduction  
Keyword(3) energy reduction  
Keyword(4) write-reduction code  
Keyword(5) error-correctin code  
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1st Author's Name Masashi Tawada  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Shinji Kimura  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Masao Yanagisawa  
3rd Author's Affiliation Waseda University (Waseda Univ.)
4th Author's Name Nozomu Togawa  
4th Author's Affiliation Waseda University (Waseda Univ.)
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Speaker
Date Time 2015-03-03 16:15:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2014-173 
Volume (vol) IEICE-114 
Number (no) no.476 
Page p.115 
#Pages IEICE-1 
Date of Issue IEICE-VLD-2015-02-23 


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