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| Presentation | 2015-03-03 09:15 A low-power soft error tolerant latch scheme Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.)  VLD2014-162 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In recent technology scaling, reduction of reliability by soft-error and increase power has appeared as an inevitable problem for logic circuits. We propose a low-power and high soft-error tolerant latch called TSPC-SEH latch based Soft Error Hardened(SEH) latch and True Single Phase Clock(TSPC). To compere SEH latch and DICE latch, the proposed latch archives 42% power reduction, and 54%s delay reduction. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Power / Radiation-Hard Redundant Latch / Dual Interlocked storage Cell (DICE) / Soft Error Hardened (SEH) Latch / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 476, VLD2014-162, pp. 55-60, March 2015. | |
| Paper # | VLD2014-162 | |
| Date of Issue | 2015-02-23 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2014-162 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2015-03-02 - 2015-03-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2015-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A low-power soft error tolerant latch scheme |
| Sub Title (in English) | |
| Keyword(1) | Power |
| Keyword(2) | Radiation-Hard Redundant Latch |
| Keyword(3) | Dual Interlocked storage Cell (DICE) |
| Keyword(4) | Soft Error Hardened (SEH) Latch |
| Keyword(5) | |
| Keyword(6) | |
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| Keyword(8) | |
| 1st Author's Name | Saki Tajima |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | Youhua Shi |
| 2nd Author's Affiliation | Waseda University (Waseda Univ.) |
| 3rd Author's Name | Nozomu Togawa |
| 3rd Author's Affiliation | Waseda University (Waseda Univ.) |
| 4th Author's Name | Masao Yanagisawa |
| 4th Author's Affiliation | Waseda University (Waseda Univ.) |
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| Speaker | Author-1 |
| Date Time | 2015-03-03 09:15:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2014-162 |
| Volume (vol) | vol.114 |
| Number (no) | no.476 |
| Page | pp.55-60 |
| #Pages | 6 |
| Date of Issue | 2015-02-23 (VLD) |
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