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| Presentation | 2015-03-03 15:50 [Memorial Lecture] Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.)  VLD2014-172 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Near-threshold computing has emerged as a promising solution for drastically improving the energy efficiency of microprocessors. This paper shows architectural-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we show several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28-nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Near-threshold computing / Statistical static timing analysis (SSTA) / / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 476, VLD2014-172, pp. 109-114, March 2015. | |
| Paper # | VLD2014-172 | |
| Date of Issue | 2015-02-23 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2014-172 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2015-03-02 - 2015-03-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2015-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design |
| Sub Title (in English) | |
| Keyword(1) | Near-threshold computing |
| Keyword(2) | Statistical static timing analysis (SSTA) |
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| 1st Author's Name | Jun Shiomi |
| 1st Author's Affiliation | Kyoto University (Kyoto Univ.) |
| 2nd Author's Name | Tohru Ishihara |
| 2nd Author's Affiliation | Kyoto University (Kyoto Univ.) |
| 3rd Author's Name | Hidetoshi Onodera |
| 3rd Author's Affiliation | Kyoto University (Kyoto Univ.) |
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| Speaker | Author-2 |
| Date Time | 2015-03-03 15:50:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2014-172 |
| Volume (vol) | vol.114 |
| Number (no) | no.476 |
| Page | pp.109-114 |
| #Pages | 6 |
| Date of Issue | 2015-02-23 (VLD) |
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