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Paper Abstract and Keywords
Presentation 2015-01-30 09:50
A feasibility study on implementing numerical applications on FPGAs using Vivado HLS
Hiroki Nakasone, Yasunori Osana, Yasunori Nagata (Univ of Ryukyu) VLD2014-135 CPSY2014-144 RECONF2014-68
Abstract (in Japanese) (See Japanese page) 
(in English) FPGAs are one of hopeful candidate of accelerator for scientific computing in near future. There are many attempts in various area of science, to build custom numerical pipelines on FPGAs to realize high-performance and low-power computing platform. However, FPGA design basically requires HDL design skills, that is not familiar with scientists in physics, life science and other field of sciences. The aim of this research is to find out an effective way to design an accelerator for scientific computation using high-level synthesis (HLS) tools, that support floating– point computation. In this report, solvers diffusion equation on 2-D orthogonal grid had implemented in both HDL and HLS as benchmark, with different ways to give boundary conditions and different methods of numerical inte- gration. As the result, the resulting circuit synthesized by Vivado HLS had reasonable size and performance. While Vivado HLS requires a little care about way of coding in C, users can try pipelining or inline expansion of loops and functions easily. Thus, it is reasonable to say that using HLS to implement kernels of scientific computation can be
an effective solution.
Keyword (in Japanese) (See Japanese page) 
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Reference Info. IEICE Tech. Rep., vol. 114, no. 428, RECONF2014-68, pp. 145-150, Jan. 2015.
Paper # RECONF2014-68 
Date of Issue 2015-01-22 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-135 CPSY2014-144 RECONF2014-68

Conference Information
Committee RECONF CPSY VLD IPSJ-SLDM  
Conference Date 2015-01-29 - 2015-01-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2015-01-RECONF-CPSY-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A feasibility study on implementing numerical applications on FPGAs using Vivado HLS 
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1st Author's Name Hiroki Nakasone  
1st Author's Affiliation University of the Ryukyus (Univ of Ryukyu)
2nd Author's Name Yasunori Osana  
2nd Author's Affiliation University of the Ryukyus (Univ of Ryukyu)
3rd Author's Name Yasunori Nagata  
3rd Author's Affiliation University of the Ryukyus (Univ of Ryukyu)
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Speaker
Date Time 2015-01-30 09:50:00 
Presentation Time 20 
Registration for RECONF 
Paper # IEICE-VLD2014-135,IEICE-CPSY2014-144,IEICE-RECONF2014-68 
Volume (vol) IEICE-114 
Number (no) no.426(VLD), no.427(CPSY), no.428(RECONF) 
Page pp.145-150 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2015-01-22,IEICE-CPSY-2015-01-22,IEICE-RECONF-2015-01-22 


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