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Paper Abstract and Keywords
Presentation 2015-01-30 15:15
MieruSys Project : Developing an Advanced Computer System with Multiple FPGAs
Yuki Matsuda, Eri Ogawa, Tomohiro Misono (Tokyo Tech), Naoki Fujieda, Shuichi Ichikawa (TUT), Kenji Kise (Tokyo Tech) VLD2014-146 CPSY2014-155 RECONF2014-79
Abstract (in Japanese) (See Japanese page) 
(in English) This paper describes the design and current development of MieruSys project which develops a future computer system with multiple FPGAs.
With the performance improvement of FPGA due to scale of process technology,
FPGA has become gradually used in the field where ASIC was employed previously.
Also, user's demands for computer systems become diversified and application specific accelerators are becoming needed.
In this MieruSys project, we design the computer components with multiple FPGAs, connect them with mesh network, and develop a whole computer system.
We name this computer system MieruSys.
Using mesh network can allow users to add accelerator components easily, and achieve high scalability.
MieruSys is in the early development stage, and currently we have MieruSys ver.0.1 which can run Linux and FreeDOS on an FPGA board.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Multiple FPGAs / Mesh / Computer System / OS / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 428, RECONF2014-79, pp. 211-216, Jan. 2015.
Paper # RECONF2014-79 
Date of Issue 2015-01-22 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-146 CPSY2014-155 RECONF2014-79

Conference Information
Committee RECONF CPSY VLD IPSJ-SLDM  
Conference Date 2015-01-29 - 2015-01-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2015-01-RECONF-CPSY-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) MieruSys Project : Developing an Advanced Computer System with Multiple FPGAs 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Multiple FPGAs  
Keyword(3) Mesh  
Keyword(4) Computer System  
Keyword(5) OS  
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Keyword(8)  
1st Author's Name Yuki Matsuda  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
2nd Author's Name Eri Ogawa  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
3rd Author's Name Tomohiro Misono  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
4th Author's Name Naoki Fujieda  
4th Author's Affiliation Toyohashi University of Technology (TUT)
5th Author's Name Shuichi Ichikawa  
5th Author's Affiliation Toyohashi University of Technology (TUT)
6th Author's Name Kenji Kise  
6th Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
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Speaker
Date Time 2015-01-30 15:15:00 
Presentation Time 20 
Registration for RECONF 
Paper # IEICE-VLD2014-146,IEICE-CPSY2014-155,IEICE-RECONF2014-79 
Volume (vol) IEICE-114 
Number (no) no.426(VLD), no.427(CPSY), no.428(RECONF) 
Page pp.211-216 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2015-01-22,IEICE-CPSY-2015-01-22,IEICE-RECONF-2015-01-22 


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