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Paper Abstract and Keywords
Presentation 2015-01-30 17:30
A Cache to Cache Communication Strategy for Wireless 3D Multi-Core Processors
Masataka Matsumura (UEC), Masaaki Kondo (Univ. Tokyo), Hiroki Matsutani (Keio Univ.), Yasutaka Wada (Waseda Univ.), Hiroki Honda (UEC) VLD2014-152 CPSY2014-161 RECONF2014-85
Abstract (in Japanese) (See Japanese page) 
(in English) The inductive-coupling 3D chip stacking technique has several advantages over TSV-based 3D stacking. For example, its manufacturing cost is less expensive than TSV-based stacking. Moreover, inductive coupling coils can be placed on top of logic gates. Making good use of this feature, we investigate a cache to cache communication mechanism to improve manycore processor performance. We evaluate the proposed mechanism with a manycore simulator and results reveal that it improves performance by 5.6% on average compared to a conventional router-based 3D stacked manycore processor.
Keyword (in Japanese) (See Japanese page) 
(in English) 3-D Stacking / Network-on-Chip / Multi-core System / TCI / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 427, CPSY2014-161, pp. 245-250, Jan. 2015.
Paper # CPSY2014-161 
Date of Issue 2015-01-22 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-152 CPSY2014-161 RECONF2014-85

Conference Information
Committee RECONF CPSY VLD IPSJ-SLDM  
Conference Date 2015-01-29 - 2015-01-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To CPSY 
Conference Code 2015-01-RECONF-CPSY-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Cache to Cache Communication Strategy for Wireless 3D Multi-Core Processors 
Sub Title (in English)  
Keyword(1) 3-D Stacking  
Keyword(2) Network-on-Chip  
Keyword(3) Multi-core System  
Keyword(4) TCI  
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1st Author's Name Masataka Matsumura  
1st Author's Affiliation The University of Electro-Communications (UEC)
2nd Author's Name Masaaki Kondo  
2nd Author's Affiliation University of Tokyo (Univ. Tokyo)
3rd Author's Name Hiroki Matsutani  
3rd Author's Affiliation Keio University (Keio Univ.)
4th Author's Name Yasutaka Wada  
4th Author's Affiliation Waseda University (Waseda Univ.)
5th Author's Name Hiroki Honda  
5th Author's Affiliation The University of Electro-Communications (UEC)
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Speaker
Date Time 2015-01-30 17:30:00 
Presentation Time 20 
Registration for CPSY 
Paper # IEICE-VLD2014-152,IEICE-CPSY2014-161,IEICE-RECONF2014-85 
Volume (vol) IEICE-114 
Number (no) no.426(VLD), no.427(CPSY), no.428(RECONF) 
Page pp.245-250 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2015-01-22,IEICE-CPSY-2015-01-22,IEICE-RECONF-2015-01-22 


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