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Paper Abstract and Keywords
Presentation 2015-01-30 14:00
Acceleration of Big Data Partitioning with Multiple FPGA boards
Ryu Kudo, Saori Sudo, Yasin Oge (UEC), Yuta Terada (AVAL DATA), Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga (UEC) VLD2014-143 CPSY2014-152 RECONF2014-76
Abstract (in Japanese) (See Japanese page) 
(in English) Data volume and diversity that we treat have been increasing rapidly because of increasing popularity of the internet and emerging sensor technologies. In order to analyze Big Data, data distribution on multiple computing nodes influences the computational time. Our research group proposes a offloading scheme of such a big data analytics process to a dedicated hardware which equips FPGA, Flash storage and network interface. This technical report describes an implementation of partitioning distribute nucleotide database for sequence similarity search in bioscience as a case study, and discusses the performance evaluation. Through the evaluation of ''est human'' database, we confirm that 24-27 times seep-up is achieved by the proposed method compared to a software-based procedure of mpiBLAST, with maintaining processor and network loads in low.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / mpiBLAST / Big Data / Partitioning / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 427, CPSY2014-152, pp. 193-198, Jan. 2015.
Paper # CPSY2014-152 
Date of Issue 2015-01-22 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-143 CPSY2014-152 RECONF2014-76

Conference Information
Conference Date 2015-01-29 - 2015-01-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To CPSY 
Conference Code 2015-01-RECONF-CPSY-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Acceleration of Big Data Partitioning with Multiple FPGA boards 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) mpiBLAST  
Keyword(3) Big Data  
Keyword(4) Partitioning  
1st Author's Name Ryu Kudo  
1st Author's Affiliation The University of Electro-Communications (UEC)
2nd Author's Name Saori Sudo  
2nd Author's Affiliation The University of Electro-Communications (UEC)
3rd Author's Name Yasin Oge  
3rd Author's Affiliation The University of Electro-Communications (UEC)
4th Author's Name Yuta Terada  
4th Author's Affiliation AVAL DATA (AVAL DATA)
5th Author's Name Masato Yoshimi  
5th Author's Affiliation The University of Electro-Communications (UEC)
6th Author's Name Hidetsugu Irie  
6th Author's Affiliation The University of Electro-Communications (UEC)
7th Author's Name Tsutomu Yoshinaga  
7th Author's Affiliation The University of Electro-Communications (UEC)
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Date Time 2015-01-30 14:00:00 
Presentation Time 20 
Registration for CPSY 
Paper # IEICE-VLD2014-143,IEICE-CPSY2014-152,IEICE-RECONF2014-76 
Volume (vol) IEICE-114 
Number (no) no.426(VLD), no.427(CPSY), no.428(RECONF) 
Page pp.193-198 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2015-01-22,IEICE-CPSY-2015-01-22,IEICE-RECONF-2015-01-22 

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