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Paper Abstract and Keywords
Presentation 2015-01-30 09:30
Implementation and Evaluation of the Low-level Communication Mechanism on FLOPS-2D
Katsuki Kyan, Makoto Arakaki, Yusuke Hirai, Hiroki Nakasone (Univ. of the Ryukyus), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.), Yasunori Osana (Univ. of the Ryukyus) VLD2014-134 CPSY2014-143 RECONF2014-67
Abstract (in Japanese) (See Japanese page) 
(in English) FLOPS-2D is a multiple-FPGA computer system that consists of several FLOPS boards. Each FLOPS board has one FPGA, memory modules and 4 high-speed serial links to connect the boards to each other. Because each FLOPS board has its own clock oscillator, slight differences of their frequencies becomes a problem on sending and receiving data between the boards. In addition, each FPGA is configured and reset individually so they need mechanism to start up after the links had established. In this report, the design and implementation of communication and start-up mechanism are shown. The mechanisms had verified by both simulation on 3x3 system and a real system of 2x2.
Keyword (in Japanese) (See Japanese page) 
(in English) FLOPS-2D / FPGA / Custom Computer / High-speed Serial Link / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 428, RECONF2014-67, pp. 139-143, Jan. 2015.
Paper # RECONF2014-67 
Date of Issue 2015-01-22 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-134 CPSY2014-143 RECONF2014-67

Conference Information
Conference Date 2015-01-29 - 2015-01-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2015-01-RECONF-CPSY-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation and Evaluation of the Low-level Communication Mechanism on FLOPS-2D 
Sub Title (in English)  
Keyword(1) FLOPS-2D  
Keyword(2) FPGA  
Keyword(3) Custom Computer  
Keyword(4) High-speed Serial Link  
1st Author's Name Katsuki Kyan  
1st Author's Affiliation University of the Ryukyus (Univ. of the Ryukyus)
2nd Author's Name Makoto Arakaki  
2nd Author's Affiliation University of the Ryukyus (Univ. of the Ryukyus)
3rd Author's Name Yusuke Hirai  
3rd Author's Affiliation University of the Ryukyus (Univ. of the Ryukyus)
4th Author's Name Hiroki Nakasone  
4th Author's Affiliation University of the Ryukyus (Univ. of the Ryukyus)
5th Author's Name Naoyuki Fujita  
5th Author's Affiliation Japan Aerospace Exploration Agency (JAXA)
6th Author's Name Hideharu Amano  
6th Author's Affiliation Keio University (Keio Univ.)
7th Author's Name Yasunori Osana  
7th Author's Affiliation University of the Ryukyus (Univ. of the Ryukyus)
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Date Time 2015-01-30 09:30:00 
Presentation Time 20 
Registration for RECONF 
Paper # IEICE-VLD2014-134,IEICE-CPSY2014-143,IEICE-RECONF2014-67 
Volume (vol) IEICE-114 
Number (no) no.426(VLD), no.427(CPSY), no.428(RECONF) 
Page pp.139-143 
#Pages IEICE-5 
Date of Issue IEICE-VLD-2015-01-22,IEICE-CPSY-2015-01-22,IEICE-RECONF-2015-01-22 

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