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| Presentation | 2015-01-29 11:05 Exploring 3D FPGA Architectures to Minimize the Number of Inter-layer Connections Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)  VLD2014-120 CPSY2014-129 RECONF2014-53 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The 3D IC technology is being researched to build better performance LSIs in a variety of applications when the process miniaturization approaches its physical limitation. This technology provides shorter logics distances and high speed wide I/Os by stacking IC layers vertically. However, because of the large performance overhead of inter-layer connections, the architecture design is challenging, especially for 3D FPGAs. In this paper, in order to balance the cost and performance, and to explore 3D FPGA architectures with realistic 3D IC processes, we propose and compare spatial distributed and function distributed 3D FPGAs. The results show that when considering a two layers 3D FPGA, a face-down stacked function distributed architecture performances better. On the other hand, face-up stacked spatial distributed architectures have more advantages when building 3D FPGAs with more than two layers. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | 3D-FPGA / TSV / / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 428, RECONF2014-53, pp. 41-46, Jan. 2015. | |
| Paper # | RECONF2014-53 | |
| Date of Issue | 2015-01-22 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2014-120 CPSY2014-129 RECONF2014-53 |
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| Conference Information | |
| Committee | RECONF CPSY VLD IPSJ-SLDM |
| Conference Date | 2015-01-29 - 2015-01-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2015-01-RECONF-CPSY-VLD-SLDM |
| Language | English (Japanese title is available) |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Exploring 3D FPGA Architectures to Minimize the Number of Inter-layer Connections |
| Sub Title (in English) | |
| Keyword(1) | 3D-FPGA |
| Keyword(2) | TSV |
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| 1st Author's Name | Qian Zhao |
| 1st Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 2nd Author's Name | Motoki Amagasaki |
| 2nd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 3rd Author's Name | Masahiro Iida |
| 3rd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 4th Author's Name | Morihiro Kuga |
| 4th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 5th Author's Name | Toshinori Sueyoshi |
| 5th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
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| Speaker | Author-1 |
| Date Time | 2015-01-29 11:05:00 |
| Presentation Time | 20 minutes |
| Registration for | RECONF |
| Paper # | VLD2014-120, CPSY2014-129, RECONF2014-53 |
| Volume (vol) | vol.114 |
| Number (no) | no.426(VLD), no.427(CPSY), no.428(RECONF) |
| Page | pp.41-46 |
| #Pages | 6 |
| Date of Issue | 2015-01-22 (VLD, CPSY, RECONF) |
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