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Paper Abstract and Keywords
Presentation 2015-01-29 09:55
NoC Architecture with Priority-based Packet Overtaking and Resource Control
Shuhei Otsuki, Keigo Mizotani, Masayoshi Takasu (Keio Univ.), Daiki Yamazaki (Sony), Nobuyuki Yamasaki (Keio Univ.) VLD2014-117 CPSY2014-126 RECONF2014-50
Abstract (in Japanese) (See Japanese page) 
(in English) With the recent advances in semiconductor technology, many transistors have been integrated into a single chip and Chip-Multiprocessors (CMPs) are common today. However, the number of cores in them has been increasing and it is difficult to support them with the traditional common bus. To solve this problem, Net-work-on-Chips (NoCs) have been researched in recent years. The load sharing by routing can reduce the transfer delay of packets and improve the performance of NoCs.
However, this technique faces the limitation on constraints of the mounting area of routers.
In this paper, we add a priority to a packet header of NoCs. We implemented
an on-chip router with a function of priority-based packet overtaking. In addition, we implemented the mechanism to prevent resource occupation caused by priority control.
Evaluation results show that the effectiveness of the priority-based packet overtaking. They also show that transfer latency of low-priority packets can be reduced while maintaining that of high-priority packets by resource control.
Keyword (in Japanese) (See Japanese page) 
(in English) Priority-based Packet Overtaking / Resource Control / Network-on-Chip / / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 427, CPSY2014-126, pp. 25-30, Jan. 2015.
Paper # CPSY2014-126 
Date of Issue 2015-01-22 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-117 CPSY2014-126 RECONF2014-50

Conference Information
Committee RECONF CPSY VLD IPSJ-SLDM  
Conference Date 2015-01-29 - 2015-01-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To CPSY 
Conference Code 2015-01-RECONF-CPSY-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) NoC Architecture with Priority-based Packet Overtaking and Resource Control 
Sub Title (in English)  
Keyword(1) Priority-based Packet Overtaking  
Keyword(2) Resource Control  
Keyword(3) Network-on-Chip  
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1st Author's Name Shuhei Otsuki  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Keigo Mizotani  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Masayoshi Takasu  
3rd Author's Affiliation Keio University (Keio Univ.)
4th Author's Name Daiki Yamazaki  
4th Author's Affiliation Sony Corporation (Sony)
5th Author's Name Nobuyuki Yamasaki  
5th Author's Affiliation Keio University (Keio Univ.)
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Speaker
Date Time 2015-01-29 09:55:00 
Presentation Time 20 
Registration for CPSY 
Paper # IEICE-VLD2014-117,IEICE-CPSY2014-126,IEICE-RECONF2014-50 
Volume (vol) IEICE-114 
Number (no) no.426(VLD), no.427(CPSY), no.428(RECONF) 
Page pp.25-30 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2015-01-22,IEICE-CPSY-2015-01-22,IEICE-RECONF-2015-01-22 


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