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Paper Abstract and Keywords
Presentation 2015-01-27 14:50
[Invited Talk] Low power and high memory density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques
Kazutaka Ikegami, Hiroki Noguchi, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Takao Ochiai, Naoharu Shimomura, Shogo Itai, Daisuke Saida, Chika Tanaka, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) Link to ES Tech. Rep. Archives: SDM2014-142
Abstract (in Japanese) (See Japanese page) 
(in English) Due to difficulty to increase clock frequency, recent processors increase cache memory to improve performance. However, leakage current and large cell size of SRAM is known to be issues. To reduce power and area simultaneously, magnetic tunneling junction (MTJ) based cache memory is considered promising. There are two issues for realizing MTJ based cache memory, one is large write current of MTJ and the other is integration with logic CMOS. In this paper, we develop three technologies to resolve these issues, low power advanced-MTJ development, low temperature integration technology and asymmetric compensation technology which utilize asymmetry of cache data. By proposed technology, cache power can be reduced 60% with only 7% performance overhead.
Keyword (in Japanese) (See Japanese page) 
(in English) MTJ / MRAM / STT-MRAM / cache memory / normally-off computing / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 421, SDM2014-142, pp. 29-32, Jan. 2015.
Paper # SDM2014-142 
Date of Issue 2015-01-20 (SDM) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Conference Information
Committee SDM  
Conference Date 2015-01-27 - 2015-01-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SDM 
Conference Code 2015-01-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Low power and high memory density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques 
Sub Title (in English)  
Keyword(1) MTJ  
Keyword(2) MRAM  
Keyword(3) STT-MRAM  
Keyword(4) cache memory  
Keyword(5) normally-off computing  
1st Author's Name Kazutaka Ikegami  
1st Author's Affiliation Toshiba Corporation (Toshiba)
2nd Author's Name Hiroki Noguchi  
2nd Author's Affiliation Toshiba Corporation (Toshiba)
3rd Author's Name Chikayoshi Kamata  
3rd Author's Affiliation Toshiba Corporation (Toshiba)
4th Author's Name Minoru Amano  
4th Author's Affiliation Toshiba Corporation (Toshiba)
5th Author's Name Keiko Abe  
5th Author's Affiliation Toshiba Corporation (Toshiba)
6th Author's Name Keiichi Kushida  
6th Author's Affiliation Toshiba Corporation (Toshiba)
7th Author's Name Takao Ochiai  
7th Author's Affiliation Toshiba Corporation (Toshiba)
8th Author's Name Naoharu Shimomura  
8th Author's Affiliation Toshiba Corporation (Toshiba)
9th Author's Name Shogo Itai  
9th Author's Affiliation Toshiba Corporation (Toshiba)
10th Author's Name Daisuke Saida  
10th Author's Affiliation Toshiba Corporation (Toshiba)
11th Author's Name Chika Tanaka  
11th Author's Affiliation Toshiba Corporation (Toshiba)
12th Author's Name Atsushi Kawasumi  
12th Author's Affiliation Toshiba Corporation (Toshiba)
13th Author's Name Hiroyuki Hara  
13th Author's Affiliation Toshiba Corporation (Toshiba)
14th Author's Name Junichi Ito  
14th Author's Affiliation Toshiba Corporation (Toshiba)
15th Author's Name Shinobu Fujita  
15th Author's Affiliation Toshiba Corporation (Toshiba)
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17th Author's Affiliation ()
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Date Time 2015-01-27 14:50:00 
Presentation Time 25 
Registration for SDM 
Paper # IEICE-SDM2014-142 
Volume (vol) IEICE-114 
Number (no) no.421 
Page pp.29-32 
#Pages IEICE-4 
Date of Issue IEICE-SDM-2015-01-20 

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