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Paper Abstract and Keywords
Presentation 2014-11-28 10:05
Optimization for gate-level pipelined self-synchrnous circuit
Atsushi Ito, Makoto Ikeda (Univ. of Tokyo) VLD2014-107 DC2014-61
Abstract (in Japanese) (See Japanese page) 
(in English) With the down-scaling, circuit which has higher robustness is demanded. Dual-pipeline self synchronous circuit have inherent robustness. However design flow for the circuit have not been automated. We investigated the optimization for gate-level-pipelined self-synchronous circuit. We synthesize combinational circuit using a synthesis library which consists of 2-input-gate and convert to 4-input-gate by using a tool for FPGA mapping.
Keyword (in Japanese) (See Japanese page) 
(in English) Gate-Level Pipeline / Self-Synchronous Circuit / Automated Design Flow / / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 328, VLD2014-107, pp. 233-238, Nov. 2014.
Paper # VLD2014-107 
Date of Issue 2014-11-19 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-107 DC2014-61

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2014-11-26 - 2014-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) B-ConPlaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2014 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Optimization for gate-level pipelined self-synchrnous circuit 
Sub Title (in English)  
Keyword(1) Gate-Level Pipeline  
Keyword(2) Self-Synchronous Circuit  
Keyword(3) Automated Design Flow  
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1st Author's Name Atsushi Ito  
1st Author's Affiliation The University of Tokyo (Univ. of Tokyo)
2nd Author's Name Makoto Ikeda  
2nd Author's Affiliation The University of Tokyo (Univ. of Tokyo)
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Speaker
Date Time 2014-11-28 10:05:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2014-107,IEICE-DC2014-61 
Volume (vol) IEICE-114 
Number (no) no.328(VLD), no.329(DC) 
Page pp.233-238 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2014-11-19,IEICE-DC-2014-11-19 


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