IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
... (for ESS/CS/ES/ISS)
Tech. Rep. Archives
... (for ES/CS)
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2014-11-28 15:35
Energy-efficient High-level Synthesis Algorithm targeting HDR-mcv Architecture with Multiple Clock Domains and Multiple Supply Voltages
Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology/Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-102 DC2014-56
Abstract (in Japanese) (See Japanese page) 
(in English) An HDR-mcv architecture, which integrates multiple supply voltages and multiple clock domains into high-level synthesis and enables us to estimate interconnection delay effects during high-level synthesis, has been proposed with the corresponding synthesis algorithm. They assign voltages and clock frequencies to huddles which are the partitions for interconnection delay estimation during high-level synthesis. However, the voltage and clock assignment may have some energy overheads due to the increased clock trees. In this paper, we propose a new HDR-mcv architecture in which supply voltages are assigned to functional logics and clock synchronization logics separately. Next, we propose a high-level synthesis algorithm for the architecture, which can assign clock frequencies and supply voltages on the bases of the placement and energy informations. Experimental results show that the proposed method achieves 50% energy-saving compared with the conventional HDR-mcv architecture and 60% energy-saving compared with the existing high-level synthesis methods.
Keyword (in Japanese) (See Japanese page) 
(in English) high-level synthesis / energy-efficient design / multiple clock domains / multiple supply voltages / interconnection delay / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 328, VLD2014-102, pp. 203-208, Nov. 2014.
Paper # VLD2014-102 
Date of Issue 2014-11-19 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-102 DC2014-56

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2014-11-26 - 2014-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) B-ConPlaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2014 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Energy-efficient High-level Synthesis Algorithm targeting HDR-mcv Architecture with Multiple Clock Domains and Multiple Supply Voltages 
Sub Title (in English)  
Keyword(1) high-level synthesis  
Keyword(2) energy-efficient design  
Keyword(3) multiple clock domains  
Keyword(4) multiple supply voltages  
Keyword(5) interconnection delay  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Shin-ya Abe  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Youhua Shi  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Kimiyoshi Usami  
3rd Author's Affiliation Shibaura Institute of Technology/Waseda University (Shibaura Institute of Technology/Waseda Univ.)
4th Author's Name Masao Yanagisawa  
4th Author's Affiliation Waseda University (Waseda Univ.)
5th Author's Name Nozomu Togawa  
5th Author's Affiliation Waseda University (Waseda Univ.)
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker
Date Time 2014-11-28 15:35:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2014-102,IEICE-DC2014-56 
Volume (vol) IEICE-114 
Number (no) no.328(VLD), no.329(DC) 
Page pp.203-208 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2014-11-19,IEICE-DC-2014-11-19 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan