IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
... (for ESS/CS/ES/ISS)
Tech. Rep. Archives
... (for ES/CS)
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2014-11-28 10:05
A Test Point Insertion Method to Reduce Capture Power Dissipation
Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) VLD2014-99 DC2014-53
Abstract (in Japanese) (See Japanese page) 
(in English) In at-speed scan testing of deep sub-micron era, high power dissipation can occur by high launch-induced switching activity when the response to a test pattern is captured by flip-flops, resulting in excessive IR drop, which may cause significant capture-induced yield loss. It is known that test pattern manipulations methods using don’t care identification and don’t care filling are effective to reduce capture power dissipation. In this paper, we propose a novel control point insertion method to reduce capture power dissipation. Control points can increase the number of don’t cares in high power test patterns. Experimental results show that the proposed method was effective for ISCAS’89 benchmark circuits.
Keyword (in Japanese) (See Japanese page) 
(in English) transition faults / capture power dissipation / control point insertion / don't care identification / don't care filling / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 329, DC2014-53, pp. 185-190, Nov. 2014.
Paper # DC2014-53 
Date of Issue 2014-11-19 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-99 DC2014-53

Conference Information
Conference Date 2014-11-26 - 2014-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) B-ConPlaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2014 -New Field of VLSI Design- 
Paper Information
Registration To DC 
Conference Code 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Test Point Insertion Method to Reduce Capture Power Dissipation 
Sub Title (in English)  
Keyword(1) transition faults  
Keyword(2) capture power dissipation  
Keyword(3) control point insertion  
Keyword(4) don't care identification  
Keyword(5) don't care filling  
1st Author's Name Yoshiyasu Takahashi  
1st Author's Affiliation Nihon University (Nihon Univ.)
2nd Author's Name Hiroshi Yamazaki  
2nd Author's Affiliation Nihon University (Nihon Univ.)
3rd Author's Name Toshinori Hosokawa  
3rd Author's Affiliation Nihon University (Nihon Univ.)
4th Author's Name Masayoshi Yoshimura  
4th Author's Affiliation Kyoto Sangyo University (Kyoto Sangyo Univ.)
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Date Time 2014-11-28 10:05:00 
Presentation Time 25 
Registration for DC 
Paper # IEICE-VLD2014-99,IEICE-DC2014-53 
Volume (vol) IEICE-114 
Number (no) no.328(VLD), no.329(DC) 
Page pp.185-190 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2014-11-19,IEICE-DC-2014-11-19 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan