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| Presentation | 2014-11-28 09:40 A Test Generation Method for Low Capture Power Using Capture Safe Test Vectors Atsushi Hirai, Toshinori Hosokawa, Yukari Yamauchi, Masayuki Arai (Nihon Univ.)  VLD2014-98 DC2014-52 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In at-speed scan testing, capture power is a serious problem because the high power dissipation that can occur when the response for a test vector is captured by flip-flops results in circuit-damaging high temperature and timing errors, which may cause significant capture-induced yield loss. Thus, the test vectors that violate capture power constraints are not able to be used for at-speed scan testing in order to prevent unnecessary yield loss. Therefore, in test generation, it is necessary to consider capture power. In this paper, we propose a new low capture power test generation method based on fault simulation using low capture power test vectors in an initial test set. The simple simulation-based method can generate a low capture power test set in a short time. Experimental results show that the use of this method reduces the number of unsafe-faults by 97% on average and shorten test generation time by 301 times on maximum compared with the conventional low capture power test generation method. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | low power / test generation / capture safe test vectors / test vector synthesis / unsafe faults / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 329, DC2014-52, pp. 179-184, Nov. 2014. | |
| Paper # | DC2014-52 | |
| Date of Issue | 2014-11-19 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2014-98 DC2014-52 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2014-11-26 - 2014-11-28 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | B-ConPlaza |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2014 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Test Generation Method for Low Capture Power Using Capture Safe Test Vectors |
| Sub Title (in English) | |
| Keyword(1) | low power |
| Keyword(2) | test generation |
| Keyword(3) | capture safe test vectors |
| Keyword(4) | test vector synthesis |
| Keyword(5) | unsafe faults |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Atsushi Hirai |
| 1st Author's Affiliation | Nihon University (Nihon Univ.) |
| 2nd Author's Name | Toshinori Hosokawa |
| 2nd Author's Affiliation | Nihon University (Nihon Univ.) |
| 3rd Author's Name | Yukari Yamauchi |
| 3rd Author's Affiliation | Nihon University (Nihon Univ.) |
| 4th Author's Name | Masayuki Arai |
| 4th Author's Affiliation | Nihon University (Nihon Univ.) |
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| Speaker | Author-1 |
| Date Time | 2014-11-28 09:40:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | VLD2014-98, DC2014-52 |
| Volume (vol) | vol.114 |
| Number (no) | no.328(VLD), no.329(DC) |
| Page | pp.179-184 |
| #Pages | 6 |
| Date of Issue | 2014-11-19 (VLD, DC) |
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