Paper Abstract and Keywords |
Presentation |
2014-11-28 16:00
An analytic evaluation on soft error immunity enhancement due to temporal triplication Ryutaro Doi, Masanori Hashimoto, Takao Onoye (Osaka Univ.) VLD2014-112 DC2014-66 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Chip-level soft error rate is increasing due to the device miniaturization and larger scale integration. Soft error is one of major factors that degrade the reliability of integrated circuits, and soft error aware design is demanded for applications that cannot allow any failures. As one of soft error countermeasures, spatial redundancy has been widely studied and adopted in real products because of the small speed overhead and the easiness of implementation. On the other hand, temporal redundancy, which is another well-known technique, is rarely adopted in practical applications and its usefulness is not quantitatively evaluated. This report analytically evaluates the soft error immunity enhancement thanks to temporal triplication. The evaluation result shows that the error rate reduction of the temporal triplication is comparable to that of the spatial triplication. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Reliability / Soft Error / Temporal Triplication / Temporal Redundancy / Spatial Triplication / Spatial Redundancy / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 329, DC2014-66, pp. 263-268, Nov. 2014. |
Paper # |
DC2014-66 |
Date of Issue |
2014-11-19 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2014-112 DC2014-66 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2014-11-26 - 2014-11-28 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
B-ConPlaza |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2014 -New Field of VLSI Design- |
Paper Information |
Registration To |
DC |
Conference Code |
2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
An analytic evaluation on soft error immunity enhancement due to temporal triplication |
Sub Title (in English) |
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Keyword(1) |
Reliability |
Keyword(2) |
Soft Error |
Keyword(3) |
Temporal Triplication |
Keyword(4) |
Temporal Redundancy |
Keyword(5) |
Spatial Triplication |
Keyword(6) |
Spatial Redundancy |
Keyword(7) |
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Keyword(8) |
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1st Author's Name |
Ryutaro Doi |
1st Author's Affiliation |
Osaka University (Osaka Univ.) |
2nd Author's Name |
Masanori Hashimoto |
2nd Author's Affiliation |
Osaka University (Osaka Univ.) |
3rd Author's Name |
Takao Onoye |
3rd Author's Affiliation |
Osaka University (Osaka Univ.) |
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Speaker |
Author-1 |
Date Time |
2014-11-28 16:00:00 |
Presentation Time |
25 minutes |
Registration for |
DC |
Paper # |
VLD2014-112, DC2014-66 |
Volume (vol) |
vol.114 |
Number (no) |
no.328(VLD), no.329(DC) |
Page |
pp.263-268 |
#Pages |
6 |
Date of Issue |
2014-11-19 (VLD, DC) |
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