Paper Abstract and Keywords |
Presentation |
2014-11-28 16:00
A High-level Synthesis Algorithm with Delay Variation Tolerance Optimization for RDR Architectures Yuta Hagio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-103 DC2014-57 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this paper, we propose a high-level synthesis algorithm with delay variation tolerance optimization for RDR architectures.
We first obtain a non-delayed scheduling/binding result and a delayed scheduling/binding result independently.
When we obtain two scheduling/binding results, we use two variation rates, the typical variation rate and the worst variation rate, and maximize them without increasing the latency.
By adding several extra functional units to vacant RDR islands, we have a delayed scheduling/binding result so that its latency cannot be increased compared with the non-delayed one.
After that, we similarize the two scheduling/binding results by repeatedly modifying their results.
We can finally realize non-delayed and delayed scheduling/binding results simultaneously on RDR architecture with almost no area/performance overheads and we can select either one of them depending on post-silicon delay variation.
Experimental results show that our algorithm successfully reduces delayed scheduling/binding latency by up to 16.7% compared with the conventional approach. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Process and Delay Variation / Post-Silicon Tuning / High-Level Synthesis / Distributed-Register Architectures / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 328, VLD2014-103, pp. 209-214, Nov. 2014. |
Paper # |
VLD2014-103 |
Date of Issue |
2014-11-19 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2014-103 DC2014-57 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2014-11-26 - 2014-11-28 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
B-ConPlaza |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2014 -New Field of VLSI Design- |
Paper Information |
Registration To |
VLD |
Conference Code |
2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A High-level Synthesis Algorithm with Delay Variation Tolerance Optimization for RDR Architectures |
Sub Title (in English) |
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Keyword(1) |
Process and Delay Variation |
Keyword(2) |
Post-Silicon Tuning |
Keyword(3) |
High-Level Synthesis |
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Distributed-Register Architectures |
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1st Author's Name |
Yuta Hagio |
1st Author's Affiliation |
Waseda University (Waseda Univ.) |
2nd Author's Name |
Masao Yanagisawa |
2nd Author's Affiliation |
Waseda University (Waseda Univ.) |
3rd Author's Name |
Nozomu Togawa |
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Waseda University (Waseda Univ.) |
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Speaker |
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Date Time |
2014-11-28 16:00:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2014-103, DC2014-57 |
Volume (vol) |
vol.114 |
Number (no) |
no.328(VLD), no.329(DC) |
Page |
pp.209-214 |
#Pages |
6 |
Date of Issue |
2014-11-19 (VLD, DC) |
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