IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2014-11-28 13:30
[Invited Talk] A 56-Gb/s Receiver Front-End with a CTLE and 1-Tap DFE in 20-nm CMOS
Yasufumi Sakai, Takayuki Shibasaki, Takumi Danjo, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura (Fujitsu LAB.) VLD2014-96 CPM2014-127 ICD2014-70 CPSY2014-84 DC2014-50 RECONF2014-45 Link to ES Tech. Rep. Archives: CPM2014-127 ICD2014-70
Abstract (in Japanese) (See Japanese page) 
(in English) To meet ever-increasing demands for computing power in data centers, data rates over 50Gbps/signal (e.g., OIF CEI-56G-VSR)will eventually be required in wireline chip-to-chip communications within and between servers. This paper shows a 56-Gb/s receiver front-end suited for baud-rate clock recovery. Sharing the comparators for the data decision and phase detection minimizes the number of comparators in the front-end and reduces the power consumption. The front-end has a continuous-time linear equalizer followed by a 1-tap speculative decision-feedback equalizer. The front-end operates at 56Gb/s with a bit error rate of less than 10-12 with a 0.4UI margin in the bathtub curve. It occupies 0.27mm2 and consumes 177mW of power from a 0.9-V supply.
Keyword (in Japanese) (See Japanese page) 
(in English) CMOS / High-Speed I/O / Phase Detector / Decision Feedback Equalizer / Comparator / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 333, ICD2014-70, pp. 27-32, Nov. 2014.
Paper # ICD2014-70 
Date of Issue 2014-11-19 (VLD, CPSY, DC, RECONF), 2014-11-20 (CPM, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-96 CPM2014-127 ICD2014-70 CPSY2014-84 DC2014-50 RECONF2014-45 Link to ES Tech. Rep. Archives: CPM2014-127 ICD2014-70

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2014-11-26 - 2014-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) B-ConPlaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2014 -New Field of VLSI Design- 
Paper Information
Registration To ICD 
Conference Code 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A 56-Gb/s Receiver Front-End with a CTLE and 1-Tap DFE in 20-nm CMOS 
Sub Title (in English)  
Keyword(1) CMOS  
Keyword(2) High-Speed I/O  
Keyword(3) Phase Detector  
Keyword(4) Decision Feedback Equalizer  
Keyword(5) Comparator  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Yasufumi Sakai  
1st Author's Affiliation Fujitsu Laboratories LTD. (Fujitsu LAB.)
2nd Author's Name Takayuki Shibasaki  
2nd Author's Affiliation Fujitsu Laboratories LTD. (Fujitsu LAB.)
3rd Author's Name Takumi Danjo  
3rd Author's Affiliation Fujitsu Laboratories LTD. (Fujitsu LAB.)
4th Author's Name Hisakatsu Yamaguchi  
4th Author's Affiliation Fujitsu Laboratories LTD. (Fujitsu LAB.)
5th Author's Name Toshihiko Mori  
5th Author's Affiliation Fujitsu Laboratories LTD. (Fujitsu LAB.)
6th Author's Name Yoichi Koyanagi  
6th Author's Affiliation Fujitsu Laboratories LTD. (Fujitsu LAB.)
7th Author's Name Hirotaka Tamura  
7th Author's Affiliation Fujitsu Laboratories LTD. (Fujitsu LAB.)
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-3 
Date Time 2014-11-28 13:30:00 
Presentation Time 60 minutes 
Registration for ICD 
Paper # VLD2014-96, CPM2014-127, ICD2014-70, CPSY2014-84, DC2014-50, RECONF2014-45 
Volume (vol) vol.114 
Number (no) no.328(VLD), no.332(CPM), no.333(ICD), no.330(CPSY), no.329(DC), no.331(RECONF) 
Page pp.167-172(VLD), pp.27-32(CPM), pp.27-32(ICD), pp.69-74(CPSY), pp.167-172(DC), pp.63-68(RECONF) 
#Pages
Date of Issue 2014-11-19 (VLD, CPSY, DC, RECONF), 2014-11-20 (CPM, ICD) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan