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Paper Abstract and Keywords
Presentation 2014-11-28 10:30
The LSI Implementation of a Memory Based Field Programmable Device for MCU Peripherals
Yoshifumi Kawamura, Naoya Okada, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.), Hiroshi Makino (OIT), Kazutami Arimoto (Okayama Prefectural Univ.) VLD2014-108 DC2014-62
Abstract (in Japanese) (See Japanese page) 
(in English) A Field Programmable Sequencer and Memory (FPSM), which is an embedded memory based programmable device for peripherals on micro controller units, has been proposed. The FPSM has the dual functions of programmable peripherals and standard memory. In this paper, implementation on the LSI is described. The FPSM, fabricated using 180-nm 1-poly and 5-metal CMOS process technology, operates at the maximum frequency of 61.5 MHz with a power supply voltage of 1.8 V. The power consumption is 1.0 mW per programmable unit at the target frequency of 50 MHz. The FPSM is one-tenth smaller than the FPGA in both the area and power consumption.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / MCU / Memory / Peripheral function / Programmable device / Sequencer / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 328, VLD2014-108, pp. 239-244, Nov. 2014.
Paper # VLD2014-108 
Date of Issue 2014-11-19 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-108 DC2014-62

Conference Information
Conference Date 2014-11-26 - 2014-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) B-ConPlaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2014 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) The LSI Implementation of a Memory Based Field Programmable Device for MCU Peripherals 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) MCU  
Keyword(3) Memory  
Keyword(4) Peripheral function  
Keyword(5) Programmable device  
Keyword(6) Sequencer  
1st Author's Name Yoshifumi Kawamura  
1st Author's Affiliation Kanazawa University (Kanazawa Univ.)
2nd Author's Name Naoya Okada  
2nd Author's Affiliation Kanazawa University (Kanazawa Univ.)
3rd Author's Name Yoshio Matsuda  
3rd Author's Affiliation Kanazawa University (Kanazawa Univ.)
4th Author's Name Tetsuya Matsumura  
4th Author's Affiliation Nihon University (Nihon Univ.)
5th Author's Name Hiroshi Makino  
5th Author's Affiliation Osaka Institute of Technology (OIT)
6th Author's Name Kazutami Arimoto  
6th Author's Affiliation Okayama Prefectural University (Okayama Prefectural Univ.)
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Date Time 2014-11-28 10:30:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2014-108,IEICE-DC2014-62 
Volume (vol) IEICE-114 
Number (no) no.328(VLD), no.329(DC) 
Page pp.239-244 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2014-11-19,IEICE-DC-2014-11-19 

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