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Paper Abstract and Keywords
Presentation 2014-11-28 09:15
Scalable and Low Latency Structure for Castle of Chips
Hiroshi Nakahara, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) CPSY2014-79
Abstract (in Japanese) (See Japanese page) 
(in English) Castle of Chips(CoC) is a chip stacking structure without chip-to-chip wired interconnection. Instead, each chip uses inductive coupling wireless through chip interconnect for both 2D and 3D direction. Conventional linear stacking method and circular stacking method have problems that the number of stacking chip is limited, and the performance is worse than that of 2D mesh connection. In this paper, we propose a new chip stacking structure for the CoC, which makes the low latency network like piling multiple meshes network, and it realizes lower latency and higher throughput than corresponding 2D mesh. Also, we proposed a routing method for this stacking structure, and proved it to be deadlock free.
Keyword (in Japanese) (See Japanese page) 
(in English) Inductive coupling interconnect / Interconnection network / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 330, CPSY2014-79, pp. 39-44, Nov. 2014.
Paper # CPSY2014-79 
Date of Issue 2014-11-19 (CPSY) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Download PDF CPSY2014-79

Conference Information
Conference Date 2014-11-26 - 2014-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) B-ConPlaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2014 -New Field of VLSI Design- 
Paper Information
Registration To CPSY 
Conference Code 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Scalable and Low Latency Structure for Castle of Chips 
Sub Title (in English)  
Keyword(1) Inductive coupling interconnect  
Keyword(2) Interconnection network  
1st Author's Name Hiroshi Nakahara  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Hiroki Matsutani  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Michihiro Koibuchi  
3rd Author's Affiliation National Institute of Informatics (NII)
4th Author's Name Hideharu Amano  
4th Author's Affiliation Keio University (Keio Univ.)
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Date Time 2014-11-28 09:15:00 
Presentation Time 25 
Registration for CPSY 
Paper # IEICE-CPSY2014-79 
Volume (vol) IEICE-114 
Number (no) no.330 
Page pp.39-44 
#Pages IEICE-6 
Date of Issue IEICE-CPSY-2014-11-19 

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