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Paper Abstract and Keywords
Presentation 2014-11-28 10:05
Implementation and Evaluation of An Accelerator based on Manymemory Network
Ryo Shimizu, Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima (NAIST) CPSY2014-81
Abstract (in Japanese) (See Japanese page) 
(in English) In this research, we focus on the data parallelization of stencil computations on a previously proposed memory-network based accelerator, named Energy-Aware Multimode Accelerator Extension (EMAX). EMAX uses
a distributed memory network and a corresponding functional unit (FU) network to exploit data reuse chance in stencil computations and achieves a minimal data movement. We design and implement a prototype chip of EMAX.
In this work, we study the scheduling of a multi-EMAX platform, and the macro-pipelining scheme in EMAX to achieve the best memory bandwidth utilization. With these techniques, EMAX achieves 4x performance per
bandwidth of GTX780 in processing stencil kernels.
Keyword (in Japanese) (See Japanese page) 
(in English) CGRA / Accelerator / Stencil / / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 330, CPSY2014-81, pp. 51-56, Nov. 2014.
Paper # CPSY2014-81 
Date of Issue 2014-11-19 (CPSY) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2014-81

Conference Information
Conference Date 2014-11-26 - 2014-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) B-ConPlaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2014 -New Field of VLSI Design- 
Paper Information
Registration To CPSY 
Conference Code 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation and Evaluation of An Accelerator based on Manymemory Network 
Sub Title (in English)  
Keyword(1) CGRA  
Keyword(2) Accelerator  
Keyword(3) Stencil  
1st Author's Name Ryo Shimizu  
1st Author's Affiliation Nara Institute of Science and Technology (NAIST)
2nd Author's Name Masakazu Tanomoto  
2nd Author's Affiliation Nara Institute of Science and Technology (NAIST)
3rd Author's Name Shinya Takamaeda-Yamazaki  
3rd Author's Affiliation Nara Institute of Science and Technology (NAIST)
4th Author's Name Jun Yao  
4th Author's Affiliation Nara Institute of Science and Technology (NAIST)
5th Author's Name Yasuhiko Nakashima  
5th Author's Affiliation Nara Institute of Science and Technology (NAIST)
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Date Time 2014-11-28 10:05:00 
Presentation Time 25 
Registration for CPSY 
Paper # IEICE-CPSY2014-81 
Volume (vol) IEICE-114 
Number (no) no.330 
Page pp.51-56 
#Pages IEICE-6 
Date of Issue IEICE-CPSY-2014-11-19 

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