Paper Abstract and Keywords |
Presentation |
2014-11-27 16:50
Accelerating finite field arithmetic with a suitable word size Aiko Iwasaki, Yuichiro Shibata, Kiyoshi Oguri, Ryuichi Harasawa (Nagasaki Univ.) RECONF2014-44 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this paper, we implement architecture to speed up $GF(2^m)$ arithmetic in Elliptic Curve Cryptography(ECC) systems as an accelerator of the soft-cores on field programmable gate arrays (FPGAs).
The number of arithmetic operations needed for the reduction processing for $GF(2^m)$ is influenced by the irreducible polynominal and the word size, so we implement the variable word size accelerator.
As a result of evaluation with it three applications, it is shown that performance is improvement to up to 10.2 times by changing the word size compared to the standard 32-bit word size.
We also implement a multiplier to use accelerator effectively on many applications.
From these results, advantage of our accelerator is shown by dividing the multiplication into several steps. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA / Finite field arithmetic / ECC / Accelerator / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 331, RECONF2014-44, pp. 57-61, Nov. 2014. |
Paper # |
RECONF2014-44 |
Date of Issue |
2014-11-19 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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RECONF2014-44 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2014-11-26 - 2014-11-28 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
B-ConPlaza |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2014 -New Field of VLSI Design- |
Paper Information |
Registration To |
RECONF |
Conference Code |
2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Accelerating finite field arithmetic with a suitable word size |
Sub Title (in English) |
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Keyword(1) |
FPGA |
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Finite field arithmetic |
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ECC |
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Accelerator |
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1st Author's Name |
Aiko Iwasaki |
1st Author's Affiliation |
Nagasaki University (Nagasaki Univ.) |
2nd Author's Name |
Yuichiro Shibata |
2nd Author's Affiliation |
Nagasaki University (Nagasaki Univ.) |
3rd Author's Name |
Kiyoshi Oguri |
3rd Author's Affiliation |
Nagasaki University (Nagasaki Univ.) |
4th Author's Name |
Ryuichi Harasawa |
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Nagasaki University (Nagasaki Univ.) |
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Speaker |
Author-1 |
Date Time |
2014-11-27 16:50:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
RECONF2014-44 |
Volume (vol) |
vol.114 |
Number (no) |
no.331 |
Page |
pp.57-61 |
#Pages |
5 |
Date of Issue |
2014-11-19 (RECONF) |
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