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| Presentation | 2014-11-27 16:00 Design and Evaluation of High-speed Serial Communication Mechanism for FPGA-based ASIC Emulator Takashi Okamoto, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)  RECONF2014-42 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The circuit scale of Application Specific Integrated Circuit（ASIC）has been increasing. Therefore the shortening of functional verification period is required. ASIC emulator using Field Programmable Gate Arrays (FPGA) is one of the fastest verification techniques. But FPGA-based ASIC emulator requires a circuit partitioning when emulating a large-scale circuit. And its emulation frequency is remarkably reduced and I/O pins are lacked. This paper proposes the FPGA-based ASIC emulator using high-speed serial communication for data communication between the FPGAs. The evaluation result shows that maximum emulation frequency of our proposed FPGA-based ASIC emulator is 6.9MHz. From the evaluation result, we estimate maximum emulation frequency is 5.2Mhz when emulating 420 million ASIC gates circuit using 9 UltraScale FPGAs. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | ASIC-emulator / FPGA / High-speed serial communication / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 331, RECONF2014-42, pp. 45-50, Nov. 2014. | |
| Paper # | RECONF2014-42 | |
| Date of Issue | 2014-11-19 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2014-42 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2014-11-26 - 2014-11-28 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | B-ConPlaza |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2014 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and Evaluation of High-speed Serial Communication Mechanism for FPGA-based ASIC Emulator |
| Sub Title (in English) | |
| Keyword(1) | ASIC-emulator |
| Keyword(2) | FPGA |
| Keyword(3) | High-speed serial communication |
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| 1st Author's Name | Takashi Okamoto |
| 1st Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 2nd Author's Name | Morihiro Kuga |
| 2nd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 3rd Author's Name | Motoki Amagasaki |
| 3rd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 4th Author's Name | Masahiro Iida |
| 4th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 5th Author's Name | Toshinori Sueyoshi |
| 5th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
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| Speaker | Author-1 |
| Date Time | 2014-11-27 16:00:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2014-42 |
| Volume (vol) | vol.114 |
| Number (no) | no.331 |
| Page | pp.45-50 |
| #Pages | 6 |
| Date of Issue | 2014-11-19 (RECONF) |
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