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| Presentation | 2014-11-26 16:40 Don't-Care Extension in Logic Synthesis for Error Tolerant Application Tomoya Inaoka, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.)  VLD2014-89 DC2014-43 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In logic synthesis for error tolerant applications, external observability don’t-cares can be freely enhanced within a given threshold. In this paper, we discuss a method for don’t-care enhancement so as to minimize the size of synthesized logic. The proposed algorithm, like [8], focuses on prime implicants of a given logic function and, unlike [8], exploits not only the expansion but also reduction of prime implications to find effective don’t-care enhancement. Experimental results show that, compared with [8], the proposed algorithm can produce smaller logic circuits with reasonable computational effort. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | logic synthesis / logic function / error rate / don't-care / prime impricant / karnaugh map / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 328, VLD2014-89, pp. 123-128, Nov. 2014. | |
| Paper # | VLD2014-89 | |
| Date of Issue | 2014-11-19 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2014-89 DC2014-43 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2014-11-26 - 2014-11-28 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | B-ConPlaza |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2014 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Don't-Care Extension in Logic Synthesis for Error Tolerant Application |
| Sub Title (in English) | |
| Keyword(1) | logic synthesis |
| Keyword(2) | logic function |
| Keyword(3) | error rate |
| Keyword(4) | don't-care |
| Keyword(5) | prime impricant |
| Keyword(6) | karnaugh map |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Tomoya Inaoka |
| 1st Author's Affiliation | Hiroshima City University (Hiroshima City Univ.) |
| 2nd Author's Name | Hideyuki Ichihara |
| 2nd Author's Affiliation | Hiroshima City University (Hiroshima City Univ.) |
| 3rd Author's Name | Tsuyoshi Iwagaki |
| 3rd Author's Affiliation | Hiroshima City University (Hiroshima City Univ.) |
| 4th Author's Name | Tomoo Inoue |
| 4th Author's Affiliation | Hiroshima City University (Hiroshima City Univ.) |
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| Speaker | Author-1 |
| Date Time | 2014-11-26 16:40:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2014-89, DC2014-43 |
| Volume (vol) | vol.114 |
| Number (no) | no.328(VLD), no.329(DC) |
| Page | pp.123-128 |
| #Pages | 6 |
| Date of Issue | 2014-11-19 (VLD, DC) |
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