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Paper Abstract and Keywords
Presentation 2014-11-26 15:35
Parallelization of Shortest Path Search on Various Platforms and Its Evaluation
Shuto Kurebayashi, Shinya Takamaeda, Jun Yao, Yasuhiko Nakashima (NAIST) CPSY2014-74
Abstract (in Japanese) (See Japanese page) 
(in English) Since graph processing has irregular control flows and memory access patterns, its acceleration by the parallelization is harder than the image processing. In this paper, we explore an appropriate computing system architecture for graph processing, in the implementation and evaluation of the shortest path search algorithm on various existing computing platforms, such as multicore, GPU and reconfigurable accelerator. The evaluation results show that enough scalability is not obtained by the parallelization on the CPU and GPU when the input graph has enough BFS parallelism capability. In contrast, the reconfigurable accelerator can achieve a speed up by exploiting the inherent parallelisms for some graph with low concurrency.
Keyword (in Japanese) (See Japanese page) 
(in English) Graph Processing / Shortest Path Search / Dijkstra / Accelerator / CGRA / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 330, CPSY2014-74, pp. 13-18, Nov. 2014.
Paper # CPSY2014-74 
Date of Issue 2014-11-19 (CPSY) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2014-74

Conference Information
Conference Date 2014-11-26 - 2014-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) B-ConPlaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2014 -New Field of VLSI Design- 
Paper Information
Registration To CPSY 
Conference Code 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Parallelization of Shortest Path Search on Various Platforms and Its Evaluation 
Sub Title (in English)  
Keyword(1) Graph Processing  
Keyword(2) Shortest Path Search  
Keyword(3) Dijkstra  
Keyword(4) Accelerator  
Keyword(5) CGRA  
1st Author's Name Shuto Kurebayashi  
1st Author's Affiliation Nara Institute of Science and Technology (NAIST)
2nd Author's Name Shinya Takamaeda  
2nd Author's Affiliation Nara Institute of Science and Technology (NAIST)
3rd Author's Name Jun Yao  
3rd Author's Affiliation Nara Institute of Science and Technology (NAIST)
4th Author's Name Yasuhiko Nakashima  
4th Author's Affiliation Nara Institute of Science and Technology (NAIST)
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Date Time 2014-11-26 15:35:00 
Presentation Time 25 
Registration for CPSY 
Paper # IEICE-CPSY2014-74 
Volume (vol) IEICE-114 
Number (no) no.330 
Page pp.13-18 
#Pages IEICE-6 
Date of Issue IEICE-CPSY-2014-11-19 

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