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Paper Abstract and Keywords
Presentation 2014-11-26 15:10
A Process-Variation-Tolerant and Low-Latency Multi-Scenario High-level Synthesis Algorithm for HDR Architectures
Koki Igawa, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-86 DC2014-40
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose a process-variation-tolerant and low-latency multi-scenario high-level synthesis algorithm for HDR architectures. We assume two scenarios, which are a typical-case scenario and a worst-case scenario, and realize them on a single chip. By using distributed-register architectures called HDR architectures, we can take into account interconnection delays in high-level syntesis. We first schedule/bind each of the scenarios independently. After that, we commonize a typical-case scenario and a worst-case scenario and synthesize a commonized scheduling/binding result. Experimental results show that our algorithm reduces the latency of typical-case scenario by up to 33% compared with previous methods.
Keyword (in Japanese) (See Japanese page) 
(in English) High-Level Synthesis / Process Variation / Interconnection Delay / Scenario / HDR Architectures / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 328, VLD2014-86, pp. 105-110, Nov. 2014.
Paper # VLD2014-86 
Date of Issue 2014-11-19 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-86 DC2014-40

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2014-11-26 - 2014-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) B-ConPlaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2014 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Process-Variation-Tolerant and Low-Latency Multi-Scenario High-level Synthesis Algorithm for HDR Architectures 
Sub Title (in English)  
Keyword(1) High-Level Synthesis  
Keyword(2) Process Variation  
Keyword(3) Interconnection Delay  
Keyword(4) Scenario  
Keyword(5) HDR Architectures  
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1st Author's Name Koki Igawa  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Shin-ya Abe  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Masao Yanagisawa  
3rd Author's Affiliation Waseda University (Waseda Univ.)
4th Author's Name Nozomu Togawa  
4th Author's Affiliation Waseda University (Waseda Univ.)
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Speaker
Date Time 2014-11-26 15:10:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2014-86,IEICE-DC2014-40 
Volume (vol) IEICE-114 
Number (no) no.328(VLD), no.329(DC) 
Page pp.105-110 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2014-11-19,IEICE-DC-2014-11-19 


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