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Paper Abstract and Keywords
Presentation 2014-11-26 14:45
Development and Evaluation of Pipelining of Heap-Sort Execution for Low-Latency Stream Data Processing
Yoshifumi Fujikawa, Tetsuro Hommura, Tadayuki Matsumura (Hitachi) CPSY2014-72
Abstract (in Japanese) (See Japanese page) 
(in English) The feature of low latency is becoming important for applications of Stream Data Processing (SDP) such as HFT, and so is matching engine in the stock exchange. Then, we begin to study the method to execute SDP with low latency on FPGA with taking up the zaraba method, a dominant process of matching engine to trade stocks as benchmark. Toward this purpose, there are two issues for the procedure to the table called “Board Information” in which data of unmatched stock orders are accumulated. that is, to determine top priority data fast for matching engine and to pipeline the procedures for consecutive orders. For these issues, we applied heap sort algorithm to this procedure, and developed the novel pipelined heap sort algorithm that can deal with large scale “Board Information”. We evaluated the latency of the zaraba method through register transfer level (RTL) simulation by using sample order data, and it was 0.10μs on average for 5M input orders/s.
Keyword (in Japanese) (See Japanese page) 
(in English) Stream Data Processing / HFT / Zaraba method / low latency / FPGA / heap sort / pipeline /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 330, CPSY2014-72, pp. 1-6, Nov. 2014.
Paper # CPSY2014-72 
Date of Issue 2014-11-19 (CPSY) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2014-11-26 - 2014-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) B-ConPlaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2014 -New Field of VLSI Design- 
Paper Information
Registration To CPSY 
Conference Code 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Development and Evaluation of Pipelining of Heap-Sort Execution for Low-Latency Stream Data Processing 
Sub Title (in English)  
Keyword(1) Stream Data Processing  
Keyword(2) HFT  
Keyword(3) Zaraba method  
Keyword(4) low latency  
Keyword(5) FPGA  
Keyword(6) heap sort  
Keyword(7) pipeline  
Keyword(8)  
1st Author's Name Yoshifumi Fujikawa  
1st Author's Affiliation Hitachi, Ltd (Hitachi)
2nd Author's Name Tetsuro Hommura  
2nd Author's Affiliation Hitachi, Ltd (Hitachi)
3rd Author's Name Tadayuki Matsumura  
3rd Author's Affiliation Hitachi, Ltd (Hitachi)
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Speaker
Date Time 2014-11-26 14:45:00 
Presentation Time 25 
Registration for CPSY 
Paper # IEICE-CPSY2014-72 
Volume (vol) IEICE-114 
Number (no) no.330 
Page pp.1-6 
#Pages IEICE-6 
Date of Issue IEICE-CPSY-2014-11-19 


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