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Paper Abstract and Keywords
Presentation 2014-11-26 14:45
Investigation of the area reduction of observation part and control part in TSV fault detection circuit
Youhei Miyamoto, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2014-72 DC2014-26
Abstract (in Japanese) (See Japanese page) 
(in English) Since delay caused by an open TSV is usually very small, it is defficult to detect. Therefore, we have proposed a TSV fault detection circuit considering the effects of adjacent TSVs. However, the previous detection circuit requires to add a FF for each TSV to select a target TSV. Therefore, the method results in large area overhead. In addition, the relation of resolution and circuit area of VDL(Vernier Delay Line) used as a delay detection circuit has not been evaluated. In this study, in order to decrease circuit area of the TSV fault detection circuit, we improved the control part using BSC(Boundary Scan Cell). In addition, we also evaluate the most suitable number of delay gates in the VDL for small circuit area.
Keyword (in Japanese) (See Japanese page) 
(in English) TSV(Through-Silicon-Via) / design for testability / delay fault / VDL(Vernier-Delay-Line) / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 329, DC2014-26, pp. 3-8, Nov. 2014.
Paper # DC2014-26 
Date of Issue 2014-11-19 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Download PDF VLD2014-72 DC2014-26

Conference Information
Conference Date 2014-11-26 - 2014-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) B-ConPlaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2014 -New Field of VLSI Design- 
Paper Information
Registration To DC 
Conference Code 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Investigation of the area reduction of observation part and control part in TSV fault detection circuit 
Sub Title (in English)  
Keyword(1) TSV(Through-Silicon-Via)  
Keyword(2) design for testability  
Keyword(3) delay fault  
Keyword(4) VDL(Vernier-Delay-Line)  
1st Author's Name Youhei Miyamoto  
1st Author's Affiliation University of Tokushima (Tokushima Univ.)
2nd Author's Name Hiroyuki Yotsuyanagi  
2nd Author's Affiliation University of Tokushima (Tokushima Univ.)
3rd Author's Name Masaki Hashizume  
3rd Author's Affiliation University of Tokushima (Tokushima Univ.)
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Date Time 2014-11-26 14:45:00 
Presentation Time 25 
Registration for DC 
Paper # IEICE-VLD2014-72,IEICE-DC2014-26 
Volume (vol) IEICE-114 
Number (no) no.328(VLD), no.329(DC) 
Page pp.3-8 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2014-11-19,IEICE-DC-2014-11-19 

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