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Paper Abstract and Keywords
Presentation 2014-11-26 17:05
Selection of Check Variables for Area-Efficient Soft-Error Tolerant Datapath Synthesis
Junghoon Oh, Mineo Kaneko (JAIST) VLD2014-90 DC2014-44
Abstract (in Japanese) (See Japanese page) 
(in English) As the device size decreases, the reliability degradation caused by soft-errors becomes one of the greatest issues in current and future LSIs. In this paper, we propose a method to synthesize soft-error tolerant application-specific datapaths via high-level synthesis. Our method is based on concurrent error detection and retry mechanism for error detection and error correction. Two most important and novel features of our method are (1) speculative resource sharing between retry parts and secondary parts for mitigating hardware/time overhead; (2) selective insertion of comparison operations which detects soft-errors for increasing the opportunity of the speculative resource sharing. From the result of datapath synthesis experiments, we found that the combination of the speculative resource sharing and the selective insertion of comparison operations achieves maximum 32.3% improvement in latency.
Keyword (in Japanese) (See Japanese page) 
(in English) soft-error / high-level synthesis / redundancy / cone-partitioning / check variable / speculative resource sharing / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 328, VLD2014-90, pp. 129-134, Nov. 2014.
Paper # VLD2014-90 
Date of Issue 2014-11-19 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-90 DC2014-44

Conference Information
Conference Date 2014-11-26 - 2014-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) B-ConPlaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2014 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Selection of Check Variables for Area-Efficient Soft-Error Tolerant Datapath Synthesis 
Sub Title (in English)  
Keyword(1) soft-error  
Keyword(2) high-level synthesis  
Keyword(3) redundancy  
Keyword(4) cone-partitioning  
Keyword(5) check variable  
Keyword(6) speculative resource sharing  
1st Author's Name Junghoon Oh  
1st Author's Affiliation Japan Advanced Institute of Science and Technology (JAIST)
2nd Author's Name Mineo Kaneko  
2nd Author's Affiliation Japan Advanced Institute of Science and Technology (JAIST)
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Date Time 2014-11-26 17:05:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2014-90,IEICE-DC2014-44 
Volume (vol) IEICE-114 
Number (no) no.328(VLD), no.329(DC) 
Page pp.129-134 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2014-11-19,IEICE-DC-2014-11-19 

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