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| Presentation | 2014-11-26 10:05 An Effective Robust Design Using Improved Checkpoint Insertion Algorithm for Suspicious Timing-Error Prediction Scheme and its Evaluations Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)  VLD2014-81 DC2014-35 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | As process technologies advance, process and delay variation causes a complex timing design and in-situ timing error correction techniques are strongly required. Suspicious timing error prediction (STEP) predicts timing errors by monitoring checkpoints by STEP circuits (STEPCs) and how to insert checkpoints is very important. We have proposed a network-flow-based checkpoint insertion algorithm for STEP.However, our algorithm may ignore long paths and insert checkpoints near the output. In this paper, we improve how to ignore short paths and set labels by estimating path lengths.Then, we can ignore only short paths and insert checkpoints into near the center of all long paths. We evaluate our algorithm by applying it to four benchmark circuits. Experimental results show that our proposed algorithm realizes an average of 1.71X overclocking compared with just inserting no STEPC. Furthermore, our improved algorithm realizes an average of 1.15X overclocking compared with our original algorithm. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Timing error prediction / robust design / delay variation / overclocking / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 328, VLD2014-81, pp. 57-62, Nov. 2014. | |
| Paper # | VLD2014-81 | |
| Date of Issue | 2014-11-19 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2014-81 DC2014-35 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2014-11-26 - 2014-11-28 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | B-ConPlaza |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2014 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Effective Robust Design Using Improved Checkpoint Insertion Algorithm for Suspicious Timing-Error Prediction Scheme and its Evaluations |
| Sub Title (in English) | |
| Keyword(1) | Timing error prediction |
| Keyword(2) | robust design |
| Keyword(3) | delay variation |
| Keyword(4) | overclocking |
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| 1st Author's Name | Shinnosuke Yoshida |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | Youhua Shi |
| 2nd Author's Affiliation | Waseda University (Waseda Univ.) |
| 3rd Author's Name | Masao Yanagisawa |
| 3rd Author's Affiliation | Waseda University (Waseda Univ.) |
| 4th Author's Name | Nozomu Togawa |
| 4th Author's Affiliation | Waseda University (Waseda Univ.) |
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| Speaker | Author-1 |
| Date Time | 2014-11-26 10:05:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2014-81, DC2014-35 |
| Volume (vol) | vol.114 |
| Number (no) | no.328(VLD), no.329(DC) |
| Page | pp.57-62 |
| #Pages | 6 |
| Date of Issue | 2014-11-19 (VLD, DC) |
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