Paper Abstract and Keywords |
Presentation |
2014-11-06 14:40
[Invited Talk]
Modeling and Simulation of Charge-Trapping Memory and Reliability Issues Takamitsu Ishihara, Naoki Yasuda, Shosuke Fujii (Toshiba) SDM2014-102 Link to ES Tech. Rep. Archives: SDM2014-102 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Charge-trapping memory is one of the most promising candidates as the next generation memory. The complicated operation mechanism requires modeling and simulation on the basis of the experiment for the systematic understanding of the operation. Write/erase and data retention characteristics are well understood by the modeling and TCAD simulation. Reliability issues are left to be focused on by modeling and simulation. As perspective, experimental results related with the reliability are presented. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Charge-Trapping Memory / Write/Erase characteristics / Modeling / Measurement / Reliability / / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 291, SDM2014-102, pp. 37-42, Nov. 2014. |
Paper # |
SDM2014-102 |
Date of Issue |
2014-10-30 (SDM) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
SDM2014-102 Link to ES Tech. Rep. Archives: SDM2014-102 |
Conference Information |
Committee |
SDM |
Conference Date |
2014-11-06 - 2014-11-07 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kikai-Shinko-Kaikan Bldg. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Process, Device, Circuit Simulation, etc. |
Paper Information |
Registration To |
SDM |
Conference Code |
2014-11-SDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Modeling and Simulation of Charge-Trapping Memory and Reliability Issues |
Sub Title (in English) |
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Keyword(1) |
Charge-Trapping Memory |
Keyword(2) |
Write/Erase characteristics |
Keyword(3) |
Modeling |
Keyword(4) |
Measurement |
Keyword(5) |
Reliability |
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1st Author's Name |
Takamitsu Ishihara |
1st Author's Affiliation |
Toshiba Corporation (Toshiba) |
2nd Author's Name |
Naoki Yasuda |
2nd Author's Affiliation |
Toshiba Corporation (Toshiba) |
3rd Author's Name |
Shosuke Fujii |
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Toshiba Corporation (Toshiba) |
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Speaker |
Author-1 |
Date Time |
2014-11-06 14:40:00 |
Presentation Time |
50 minutes |
Registration for |
SDM |
Paper # |
SDM2014-102 |
Volume (vol) |
vol.114 |
Number (no) |
no.291 |
Page |
pp.37-42 |
#Pages |
6 |
Date of Issue |
2014-10-30 (SDM) |
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