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Paper Abstract and Keywords
Presentation 2014-09-18 14:10
Prototype of fault tolerant FPGA using 65nm CMOS process
Motoki Amagasaki, Takuya Kajiwara, Kentaro Fujisawa, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-18
Abstract (in Japanese) (See Japanese page) 
(in English) 我々はSoC(System on a Chip)に搭載されるFPGA-IP(Field Programmable Gate Array Intellectual
Property)コアに焦点をあてたFT-FPGA(Fault Tolerant FPGA)アーキテクチャの研究を行っている.信頼性が
要求されるシステムではTMR(Tripple Module Redundancy)のように対象モジュールの多重化が使われることが
多い.しかし,SoC に搭載されるFPGA-IP コアを対象とした場合,面積制約が非常に大きいため単純な冗長化は困
難であることが多い.我々の提案するFT-FPGA は決まったタイル数毎にスペアタイルを備え,故障が起きた際に回
路を退避させることで信頼性を上げている.また,FT-FPGA はソフトIP コアとして提供されるため,通常のASIC
(Application Speci c Integrate Circuit)設計ツールを用いてSoC に搭載可能である.本論文ではFT-FPGA アーキ
テクチャの探索を行い,TSMC 65nmCMOS スタンダードセルライブラリを用いてチップ試作を行った.
Keyword (in Japanese) (See Japanese page) 
(in English) FT-FPGA / IP core / Prototype Chip / / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 223, RECONF2014-18, pp. 7-12, Sept. 2014.
Paper # RECONF2014-18 
Date of Issue 2014-09-11 (RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2014-18

Conference Information
Committee RECONF  
Conference Date 2014-09-18 - 2014-09-19 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2014-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Prototype of fault tolerant FPGA using 65nm CMOS process 
Sub Title (in English)  
Keyword(1) FT-FPGA  
Keyword(2) IP core  
Keyword(3) Prototype Chip  
1st Author's Name Motoki Amagasaki  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Takuya Kajiwara  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Kentaro Fujisawa  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ.)
4th Author's Name Qian Zhao  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
5th Author's Name Masahiro Iida  
5th Author's Affiliation Kumamoto University (Kumamoto Univ.)
6th Author's Name Morihiro Kuga  
6th Author's Affiliation Kumamoto University (Kumamoto Univ.)
7th Author's Name Toshinori Sueyoshi  
7th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Date Time 2014-09-18 14:10:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-RECONF2014-18 
Volume (vol) IEICE-114 
Number (no) no.223 
Page pp.7-12 
#Pages IEICE-6 
Date of Issue IEICE-RECONF-2014-09-11 

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