Paper Abstract and Keywords |
Presentation |
2014-09-18 16:10
Dynamically reconfigurable protocol-processing hardware for communications SoC Saki Hatta, Nobuyuki Tanaka, Satoshi Shigematsu (NTT) RECONF2014-22 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We propose an architecture of dynamically reconfigurable hardware for protocol processing (DRHPP) for a communications system on a chip (SoC) in access networks to provide flexibility with high area efficiency. The DRHPP enables the modification and addition of various communications-protocol-processing functions. Our architecture consists of three types of cells. The optimized number of these types of cells for the intended protocol processing can be implemented for increasing cell-utilization efficiency, which can decrease the total area. Additionally, the best granularity for the cell also contributes to a decrease of the total area. We implemented a protocol-processing circuit using DRHPP for protocol-frame parser processing. Implementation results show the proposed architecture improves flexibility with only a 33% area penalty in comparison with a hard-wired protocol-processing circuit. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
communications-protocol processing / area efficiency / optimized cell / comminications SoC / access networks / / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 223, RECONF2014-22, pp. 29-34, Sept. 2014. |
Paper # |
RECONF2014-22 |
Date of Issue |
2014-09-11 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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RECONF2014-22 |
Conference Information |
Committee |
RECONF |
Conference Date |
2014-09-18 - 2014-09-19 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
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Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Reconfigurable Systems, etc. |
Paper Information |
Registration To |
RECONF |
Conference Code |
2014-09-RECONF |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Dynamically reconfigurable protocol-processing hardware for communications SoC |
Sub Title (in English) |
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Keyword(1) |
communications-protocol processing |
Keyword(2) |
area efficiency |
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optimized cell |
Keyword(4) |
comminications SoC |
Keyword(5) |
access networks |
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1st Author's Name |
Saki Hatta |
1st Author's Affiliation |
Nippon Telegraph and Telephone Corporation (NTT) |
2nd Author's Name |
Nobuyuki Tanaka |
2nd Author's Affiliation |
Nippon Telegraph and Telephone Corporation (NTT) |
3rd Author's Name |
Satoshi Shigematsu |
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Nippon Telegraph and Telephone Corporation (NTT) |
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Speaker |
Author-1 |
Date Time |
2014-09-18 16:10:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
RECONF2014-22 |
Volume (vol) |
vol.114 |
Number (no) |
no.223 |
Page |
pp.29-34 |
#Pages |
6 |
Date of Issue |
2014-09-11 (RECONF) |
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