Paper Abstract and Keywords |
Presentation |
2014-08-04 13:55
[Invited Talk]
STT-MRAM Development for Embedded Cache Memory Toshihiro Sugii, Yoshihisa Iba, Masaki Aoki, Hideyuki Noshiro, Koji Tsunoda, Akiyoshi Hatada, Masaaki Nakabayashi, Yuuichi Yamazaki, Atsushi Takahashi, Chikako Yoshida (LEAP) SDM2014-68 ICD2014-37 Link to ES Tech. Rep. Archives: SDM2014-68 ICD2014-37 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We report the current status of our development of spin-transfer torque magnetic RAMs (STT-MRAMs) and their integration with the back-end-of-line (BEOL) process to replace conventional embedded SRAM cache memories. In order to enhance CPU performance, it is very effective to increase cache memory capacity. If we can reduce the switching current, we can reduce MRAM cell size and increase memory capacity. To reduce the switching current, shrinking MTJ is effective. On the other hand, under the same lithography technology, the smaller the MTJ, the larger the variation in MTJ size. This paper describes the new process for fabricating smaller MTJs for high density RAMs without increasing MTJ size variation. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Spin transfer torque / STT-MRAM / MTJ / Low power / Embedded / BEOL / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 174, SDM2014-68, pp. 35-38, Aug. 2014. |
Paper # |
SDM2014-68 |
Date of Issue |
2014-07-28 (SDM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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SDM2014-68 ICD2014-37 Link to ES Tech. Rep. Archives: SDM2014-68 ICD2014-37 |
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