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Paper Abstract and Keywords
Presentation 2014-08-04 10:50
A 28nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor with 2GHz Cores and Low-Power 1GHz Cores
Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Hiroshi Kishibe, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori (Renesas Electronics) Link to ES Tech. Rep. Archives: SDM2014-64 ICD2014-33
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents power management and low power techniques of our heterogeneous quad/octa-core mobile application processor (AP). This AP has a combination of high-performance 2 GHz cores and energy-efficient 1 GHz cores. The maximum performance in the octa-core configuration is 35,600 DMIPS. The key design highlights are: 1) Using a dedicated PLL and H-tree clock in the high-performance CPU achieves both 2GHz operation and reduced dynamic power. 2) A low-leakage SRAM in a 28nm High-k/MG process is used and the leakage current of the peripheral circuits of the SRAM macro is optimized via multiple threshold voltages (Vt) and gate lengths (Lg), result in 24% leakage reduction of L1 cache. 3) The effects of process and voltage variations are accurately corrected by an on-chip process sensor and direct sensing of the voltage in the power mesh of the chip. 20% dynamic power reduction, 29% leakage power reduction and 40mV improvement of minimum operation voltage are achieved. 4) An enhanced CPU clock control mechanism is employed, which uses an on-chip delay sensor to reduce AC IR drop. 5) The heterogeneous CPU architecture maintains high performance even during thermal throttling.
Keyword (in Japanese) (See Japanese page) 
(in English) Heterogeneous CPU architecture / H-tree clock structure / Adaptive voltage scaling (AVS) / Dynamic Frequency Scaling (DFS) / Thermal control technique / Multi-Vt / Multi-Lg /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 175, ICD2014-33, pp. 11-16, Aug. 2014.
Paper # ICD2014-33 
Date of Issue 2014-07-28 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Conference Information
Committee ICD SDM  
Conference Date 2014-08-04 - 2014-08-05 
Place (in Japanese) (See Japanese page) 
Place (in English) Hokkaido Univ., Multimedia Education Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2014-08-ICD-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A 28nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor with 2GHz Cores and Low-Power 1GHz Cores 
Sub Title (in English)  
Keyword(1) Heterogeneous CPU architecture  
Keyword(2) H-tree clock structure  
Keyword(3) Adaptive voltage scaling (AVS)  
Keyword(4) Dynamic Frequency Scaling (DFS)  
Keyword(5) Thermal control technique  
Keyword(6) Multi-Vt  
Keyword(7) Multi-Lg  
Keyword(8)  
1st Author's Name Mitsuhiko Igarashi  
1st Author's Affiliation Renesas Electronics corporation (Renesas Electronics)
2nd Author's Name Toshifumi Uemura  
2nd Author's Affiliation Renesas Electronics corporation (Renesas Electronics)
3rd Author's Name Ryo Mori  
3rd Author's Affiliation Renesas Electronics corporation (Renesas Electronics)
4th Author's Name Hiroshi Kishibe  
4th Author's Affiliation Renesas Electronics corporation (Renesas Electronics)
5th Author's Name Masaaki Taniguchi  
5th Author's Affiliation Renesas Electronics corporation (Renesas Electronics)
6th Author's Name Kohei Wakahara  
6th Author's Affiliation Renesas Electronics corporation (Renesas Electronics)
7th Author's Name Toshiharu Saito  
7th Author's Affiliation Renesas Electronics corporation (Renesas Electronics)
8th Author's Name Masaki Fujigaya  
8th Author's Affiliation Renesas Electronics corporation (Renesas Electronics)
9th Author's Name Kazuki Fukuoka  
9th Author's Affiliation Renesas Electronics corporation (Renesas Electronics)
10th Author's Name Koji Nii  
10th Author's Affiliation Renesas Electronics corporation (Renesas Electronics)
11th Author's Name Takeshi Kataoka  
11th Author's Affiliation Renesas Electronics corporation (Renesas Electronics)
12th Author's Name Toshihiro Hattori  
12th Author's Affiliation Renesas Electronics corporation (Renesas Electronics)
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Speaker
Date Time 2014-08-04 10:50:00 
Presentation Time 25 
Registration for ICD 
Paper # IEICE-SDM2014-64,IEICE-ICD2014-33 
Volume (vol) IEICE-114 
Number (no) no.174(SDM), no.175(ICD) 
Page pp.11-16 
#Pages IEICE-6 
Date of Issue IEICE-SDM-2014-07-28,IEICE-ICD-2014-07-28 


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