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Paper Abstract and Keywords
Presentation 2014-08-01 13:30
[Invited Talk] InGaAs MOSFET Source Structures Toward High Speed/low Power Applications
Yasuyuki Miyamoto, Toru Kanazawa, Yoshiharu Yonai, Atsushi Kato, Motohiko Fujimatsu, Masashi Kashiwano, Kazuto Ohsawa, Kazumi Ohashi (Tokyo Inst. of Tech.) ED2014-56 Link to ES Tech. Rep. Archives: ED2014-56
Abstract (in Japanese) (See Japanese page) 
(in English) Abstract High on-currents (I_{on}) and low off-currents (I_{off}) under low supply voltage are important for logic applications. A heavily doped InP source was introduced to demonstrate the existence of high I_{on} in InGaAs MOSFETs, and I_D = 2.4 mA/$myu$m at V_D = 0.5 V was observed. GaAsSb source was introduced in InGaAs tunnel FET to realize low I_{off}. Narrow channel body was found to be essential for steep sub-threshold (SS) dependence, and a fabricated GaAsSb/InGaAs vertical tunnel FET with a 26 nm wide body showed steep SS. In addition, an InGaAs/InP super-lattice source was studied to consider the possibility of simultaneous high I_{on} and low I_{off} realization.
Keyword (in Japanese) (See Japanese page) 
(in English) InGaAs MOSFETs / Source structure / Tunnel FET / Super-lattice source / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 168, ED2014-56, pp. 19-24, Aug. 2014.
Paper # ED2014-56 
Date of Issue 2014-07-25 (ED) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
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Download PDF ED2014-56 Link to ES Tech. Rep. Archives: ED2014-56

Conference Information
Committee ED  
Conference Date 2014-08-01 - 2014-08-01 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. B3-1 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Semiconductor Process and Devices (surface, interface, reliability), others 
Paper Information
Registration To ED 
Conference Code 2014-08-ED 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) InGaAs MOSFET Source Structures Toward High Speed/low Power Applications 
Sub Title (in English)  
Keyword(1) InGaAs MOSFETs  
Keyword(2) Source structure  
Keyword(3) Tunnel FET  
Keyword(4) Super-lattice source  
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1st Author's Name Yasuyuki Miyamoto  
1st Author's Affiliation Tokyo Institute of Technoloy (Tokyo Inst. of Tech.)
2nd Author's Name Toru Kanazawa  
2nd Author's Affiliation Tokyo Institute of Technoloy (Tokyo Inst. of Tech.)
3rd Author's Name Yoshiharu Yonai  
3rd Author's Affiliation Tokyo Institute of Technoloy (Tokyo Inst. of Tech.)
4th Author's Name Atsushi Kato  
4th Author's Affiliation Tokyo Institute of Technoloy (Tokyo Inst. of Tech.)
5th Author's Name Motohiko Fujimatsu  
5th Author's Affiliation Tokyo Institute of Technoloy (Tokyo Inst. of Tech.)
6th Author's Name Masashi Kashiwano  
6th Author's Affiliation Tokyo Institute of Technoloy (Tokyo Inst. of Tech.)
7th Author's Name Kazuto Ohsawa  
7th Author's Affiliation Tokyo Institute of Technoloy (Tokyo Inst. of Tech.)
8th Author's Name Kazumi Ohashi  
8th Author's Affiliation Tokyo Institute of Technoloy (Tokyo Inst. of Tech.)
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Speaker
Date Time 2014-08-01 13:30:00 
Presentation Time 50 
Registration for ED 
Paper # IEICE-ED2014-56 
Volume (vol) IEICE-114 
Number (no) no.168 
Page pp.19-24 
#Pages IEICE-6 
Date of Issue IEICE-ED-2014-07-25 


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