Paper Abstract and Keywords |
Presentation |
2014-07-29 10:45
Interconnect Design for Low Latency, High Topological Embeddability and Partitioning Capability by Supplementary Optical Circuit Switches Ryuta Kawano (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII) CPSY2014-20 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper focuses on how to efficiently run multiple small parallel applications in a single High-performance computing (HPC) system. As parallel applications can be optimized for several specific topologies, some of them cannot show full performance when a given physical topology is different from the logical topologies they assumed. Previously we proposed to supplementally use optical circuit switches (OCSes) to patch the electrically-switched network that achieves low latency and supports high topology partitionability, so that the electrically-switched topology efficiently embed or emulate k-ary n-cubes, fat trees and random connections. In this report we evaluate the baseline electrically-switched network topology and the embedded method in detail. Our emperical results show that the proposed topology achieves high topology embeddability, the overall low latency and a low-cost implementation compared to the conventional topologies. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
High-performance computing (HPC) / optical circuit switching / network topology / interconnection networks / datacenter networks / / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 155, CPSY2014-20, pp. 61-66, July 2014. |
Paper # |
CPSY2014-20 |
Date of Issue |
2014-07-21 (CPSY) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CPSY2014-20 |
Conference Information |
Committee |
CPSY DC |
Conference Date |
2014-07-28 - 2014-07-30 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Toki Messe, Niigata |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Parallel, Distributed and Cooperative Processing |
Paper Information |
Registration To |
CPSY |
Conference Code |
2014-07-CPSY-DC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Interconnect Design for Low Latency, High Topological Embeddability and Partitioning Capability by Supplementary Optical Circuit Switches |
Sub Title (in English) |
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Keyword(1) |
High-performance computing (HPC) |
Keyword(2) |
optical circuit switching |
Keyword(3) |
network topology |
Keyword(4) |
interconnection networks |
Keyword(5) |
datacenter networks |
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1st Author's Name |
Ryuta Kawano |
1st Author's Affiliation |
Keio University (Keio Univ.) |
2nd Author's Name |
Ikki Fujiwara |
2nd Author's Affiliation |
National Institute of Informatics (NII) |
3rd Author's Name |
Hiroki Matsutani |
3rd Author's Affiliation |
Keio University (Keio Univ.) |
4th Author's Name |
Hideharu Amano |
4th Author's Affiliation |
Keio University (Keio Univ.) |
5th Author's Name |
Michihiro Koibuchi |
5th Author's Affiliation |
National Institute of Informatics (NII) |
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Speaker |
Author-1 |
Date Time |
2014-07-29 10:45:00 |
Presentation Time |
25 minutes |
Registration for |
CPSY |
Paper # |
CPSY2014-20 |
Volume (vol) |
vol.114 |
Number (no) |
no.155 |
Page |
pp.61-66 |
#Pages |
6 |
Date of Issue |
2014-07-21 (CPSY) |
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