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Paper Abstract and Keywords
Presentation 2014-07-21 14:30
Digital Circuit Implementation of a Cost Calculation for Partial-update Exponential Chaotic Tabu Search Hardware Systems
Takeshi Miura, Masato Ozawa, Takemori Orima, Yoshihiko Horio (Tokyo Denki Univ.) NLP2014-34
Abstract (in Japanese) (See Japanese page) 
(in English) The exponential chaotic tabu search is an efficient meta-heuristic algorithm for combinatorial optimization problems. Based on this algorithm, we proposed a partial-update exponential chaotic tabu search algorithm, suitable for a compact and efficient hardware implementation. In hardware implementation of the partial-update exponential chaotic tabu search system to solve a quadratic assignment problem (QAP), we will use a digital circuit to calculate the value of the cost function of the QAP, because an analog circuit will have difficulty for this calculation. However, the digital circuitry processes sequentially, so that the digital calculation would be a bottleneck for the speed of the system. In this paper, we propose a quick cost calculation method with digital circuitry. We compare a DSP and a FPGA to implement the cost calculation. As a result, we show that the FPGA with pipeline processing is more feasible than the DSP.
Keyword (in Japanese) (See Japanese page) 
(in English) Combinatorial Optimization Problem / Quadratic Assignment Problem / Chaotic Tabu Search / Chaotic Neural Network / Field-Programmable Gate Array / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 145, NLP2014-34, pp. 17-22, July 2014.
Paper # NLP2014-34 
Date of Issue 2014-07-14 (NLP) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF NLP2014-34

Conference Information
Committee NLP  
Conference Date 2014-07-21 - 2014-07-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Hakodate City Central Library 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Nonlinear Problems, etc. 
Paper Information
Registration To NLP 
Conference Code 2014-07-NLP 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Digital Circuit Implementation of a Cost Calculation for Partial-update Exponential Chaotic Tabu Search Hardware Systems 
Sub Title (in English)  
Keyword(1) Combinatorial Optimization Problem  
Keyword(2) Quadratic Assignment Problem  
Keyword(3) Chaotic Tabu Search  
Keyword(4) Chaotic Neural Network  
Keyword(5) Field-Programmable Gate Array  
1st Author's Name Takeshi Miura  
1st Author's Affiliation Tokyo Denki University (Tokyo Denki Univ.)
2nd Author's Name Masato Ozawa  
2nd Author's Affiliation Tokyo Denki University (Tokyo Denki Univ.)
3rd Author's Name Takemori Orima  
3rd Author's Affiliation Tokyo Denki University (Tokyo Denki Univ.)
4th Author's Name Yoshihiko Horio  
4th Author's Affiliation Tokyo Denki University (Tokyo Denki Univ.)
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Date Time 2014-07-21 14:30:00 
Presentation Time 25 
Registration for NLP 
Paper # IEICE-NLP2014-34 
Volume (vol) IEICE-114 
Number (no) no.145 
Page pp.17-22 
#Pages IEICE-6 
Date of Issue IEICE-NLP-2014-07-14 

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