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| Presentation | 2014-07-11 13:40 Write Reduction of Internal Registers for Non-volatile RISC Processors Tomoya Goto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.)  CAS2014-40 VLD2014-49 SIP2014-61 MSS2014-40 SIS2014-40 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Recently next-generation non-volatile memories based on MTJ (Magnetic Tunnel Junction) have been paid attention because of their enough endurance and fast access speed. The access speed is comparable with that of CMOS memory devices but their writing energy is far larger than the energy of CMOS memory devices. So the reduction of writing operations is very important. In this study, we propose write-reduction methods depending on the types of internal registers for RISC processors. By considering the types, the control circuit can be reduced. For the register file, write operations are reduced by using "write aware flags" and "sign extension flags". For the program counter, write operations are reduced by using "XOR-based comparison" and "carry detection". The proposed method is applied to the MIPS32 processor and the write activity has been evaluated using a simulator. The write activity can be reduced about 93.1-93.8% on register files and about 54.5-56.8% on the program counter. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Next-generation non-volatile memory / MRAM(Magnetoresistive RAM) / non-volatile register file / non-volatile program counter / XOR-based clock gating control / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 123, VLD2014-49, pp. 213-218, July 2014. | |
| Paper # | VLD2014-49 | |
| Date of Issue | 2014-07-02 (CAS, VLD, SIP, MSS, SIS) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CAS2014-40 VLD2014-49 SIP2014-61 MSS2014-40 SIS2014-40 |
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| Conference Information | |
| Committee | CAS SIP MSS VLD SIS |
| Conference Date | 2014-07-09 - 2014-07-11 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hokkaido University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System, signal processing and related topics |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2014-07-CAS-SIP-MSS-VLD-SIS |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Write Reduction of Internal Registers for Non-volatile RISC Processors |
| Sub Title (in English) | |
| Keyword(1) | Next-generation non-volatile memory |
| Keyword(2) | MRAM(Magnetoresistive RAM) |
| Keyword(3) | non-volatile register file |
| Keyword(4) | non-volatile program counter |
| Keyword(5) | XOR-based clock gating control |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Tomoya Goto |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | Masao Yanagisawa |
| 2nd Author's Affiliation | Waseda University (Waseda Univ.) |
| 3rd Author's Name | Shinji Kimura |
| 3rd Author's Affiliation | Waseda University (Waseda Univ.) |
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| Speaker | Author-1 |
| Date Time | 2014-07-11 13:40:00 |
| Presentation Time | 20 minutes |
| Registration for | VLD |
| Paper # | CAS2014-40, VLD2014-49, SIP2014-61, MSS2014-40, SIS2014-40 |
| Volume (vol) | vol.114 |
| Number (no) | no.122(CAS), no.123(VLD), no.124(SIP), no.125(MSS), no.126(SIS) |
| Page | pp.213-218 |
| #Pages | 6 |
| Date of Issue | 2014-07-02 (CAS, VLD, SIP, MSS, SIS) |
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