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Paper Abstract and Keywords
Presentation 2014-07-11 15:10
A distributed asynchronous arbiter for ring segmented bus type GALS systems
Yoshiki Odagiri, Masaki Akari (Okayama Prefectural Univ.), Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Tomoyuki Yokogawa, Yoichiro Sato, Kazutami Arimoto (Okayama Prefectural Univ.) CAS2014-44 VLD2014-53 SIP2014-65 MSS2014-44 SIS2014-44
Abstract (in Japanese) (See Japanese page) 
(in English) A ring segmented bus (RSB) which connects the divided annular bus dynamically has been proposed for GALS systems. However, the scalability of RSB is particularly poor, because a global arbiter (GArb) in RSB is constructed as the centralized type. In this study,we proposed a structure of decentralized GArb having an ability to control the buses. This arbiter can easily perform the addition of Clock Domains (CDs), because it constructed with a celles which is arranged for each of CDs of GALS system. On RSB, it is necessary to derive a shortest data path from two constructible ones. In the arbiter, a path signal can be transmitted in two directions on the annular bus, and the shortest path is calculated by its wire delay. We designed the GArb by petrify which is a tool for synthesis of asynchronous circuit, and confirmed its operation by behavior simulation.
Keyword (in Japanese) (See Japanese page) 
(in English) GALS system / asynchronous circuit / arbiter / bus architecture / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 123, VLD2014-53, pp. 237-242, July 2014.
Paper # VLD2014-53 
Date of Issue 2014-07-02 (CAS, VLD, SIP, MSS, SIS) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CAS2014-44 VLD2014-53 SIP2014-65 MSS2014-44 SIS2014-44

Conference Information
Conference Date 2014-07-09 - 2014-07-11 
Place (in Japanese) (See Japanese page) 
Place (in English) Hokkaido University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System, signal processing and related topics 
Paper Information
Registration To VLD 
Conference Code 2014-07-CAS-SIP-MSS-VLD-SIS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A distributed asynchronous arbiter for ring segmented bus type GALS systems 
Sub Title (in English)  
Keyword(1) GALS system  
Keyword(2) asynchronous circuit  
Keyword(3) arbiter  
Keyword(4) bus architecture  
1st Author's Name Yoshiki Odagiri  
1st Author's Affiliation Okayama Prefectural University (Okayama Prefectural Univ.)
2nd Author's Name Masaki Akari  
2nd Author's Affiliation Okayama Prefectural University (Okayama Prefectural Univ.)
3rd Author's Name Masafumi Kondo  
3rd Author's Affiliation Kawasaki University of Medical Welfare (Kawasaki Univ. of Medical Welfare)
4th Author's Name Tomoyuki Yokogawa  
4th Author's Affiliation Okayama Prefectural University (Okayama Prefectural Univ.)
5th Author's Name Yoichiro Sato  
5th Author's Affiliation Okayama Prefectural University (Okayama Prefectural Univ.)
6th Author's Name Kazutami Arimoto  
6th Author's Affiliation Okayama Prefectural University (Okayama Prefectural Univ.)
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Date Time 2014-07-11 15:10:00 
Presentation Time 20 
Registration for VLD 
Paper # IEICE-CAS2014-44,IEICE-VLD2014-53,IEICE-SIP2014-65,IEICE-MSS2014-44,IEICE-SIS2014-44 
Volume (vol) IEICE-114 
Number (no) no.122(CAS), no.123(VLD), no.124(SIP), no.125(MSS), no.126(SIS) 
Page pp.237-242 
#Pages IEICE-6 
Date of Issue IEICE-CAS-2014-07-02,IEICE-VLD-2014-07-02,IEICE-SIP-2014-07-02,IEICE-MSS-2014-07-02,IEICE-SIS-2014-07-02 

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