Paper Abstract and Keywords |
Presentation |
2014-06-20 15:10
A Fault Tolerant Response Analyzer for Built-in Self-test Yuki Fukazawa (Mie Univ.), Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2014-14 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Reliable built-in self-test (Reliable BIST) is a scheme in which embedded BIST circuits are designed to be tolerant of their faults.
Reliable BIST is especially important for highly reliable testing not only in the production test but also in the field test; it is required to recover itself from transient errors of its embedded BIST circuits.
In this paper, we propose a self-error-correctable response analyzer (RA) for a reliable BIST scheme.
The proposed RA, called SECRA, can correct (or mask) errors that occur on itself during testing circuits-under-test (CUTs), so that it can enhance its test-reliability, which is the probability that the RA can generate the correct (expected) signature at the last test cycle.
Experimental results show that SECRA can achieve higher test-reliability compared with a general RA for some benchmark circuits. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Fault tolerance / response analyzers / test-reliability / cyclic code / transient faults / / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 99, DC2014-14, pp. 27-32, June 2014. |
Paper # |
DC2014-14 |
Date of Issue |
2014-06-13 (DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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DC2014-14 |
Conference Information |
Committee |
DC |
Conference Date |
2014-06-20 - 2014-06-20 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kikai-Shinko-Kaikan Bldg. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design/Test/Verification |
Paper Information |
Registration To |
DC |
Conference Code |
2014-06-DC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Fault Tolerant Response Analyzer for Built-in Self-test |
Sub Title (in English) |
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Keyword(1) |
Fault tolerance |
Keyword(2) |
response analyzers |
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test-reliability |
Keyword(4) |
cyclic code |
Keyword(5) |
transient faults |
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1st Author's Name |
Yuki Fukazawa |
1st Author's Affiliation |
Mie University (Mie Univ.) |
2nd Author's Name |
Hideyuki Ichihara |
2nd Author's Affiliation |
Hiroshima City University (Hiroshima City Univ.) |
3rd Author's Name |
Tomoo Inoue |
3rd Author's Affiliation |
Hiroshima City University (Hiroshima City Univ.) |
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Speaker |
Author-1 |
Date Time |
2014-06-20 15:10:00 |
Presentation Time |
25 minutes |
Registration for |
DC |
Paper # |
DC2014-14 |
Volume (vol) |
vol.114 |
Number (no) |
no.99 |
Page |
pp.27-32 |
#Pages |
6 |
Date of Issue |
2014-06-13 (DC) |
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