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Paper Abstract and Keywords
Presentation 2014-06-12 15:35
Implementation of a RISC Processor with a Complex Instruction Accelerator -- Return to a CISC --
Ryota Suzuki (Tokyo Univ. of Agriculture and Tech.), Takefumi Miyoshi (e-trees), Hironori Nakajo (Tokyo Univ. of Agriculture and Tech.) RECONF2014-13
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose a RISC processor with an accelerator which can execute a complex instruction
with a co-processor function. We have implemented this mechanism into a processor which has a lower compati-
ble subset of MIPS ISA in which existing instructions for a co-processor can be available. The mechanism allows
the processor to utilize an accelerator without modi cation of an assembler and a compiler. We show evaluated
performance gain with comparing a conventional RISC processor with our proposed processor.
Keyword (in Japanese) (See Japanese page) 
(in English) Hardware Accelerator / Processor architecture / Co-processor / FPGA / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 75, RECONF2014-13, pp. 67-72, June 2014.
Paper # RECONF2014-13 
Date of Issue 2014-06-04 (RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2014-13

Conference Information
Committee RECONF  
Conference Date 2014-06-11 - 2014-06-12 
Place (in Japanese) (See Japanese page) 
Place (in English) Katahira Sakura Hall 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2014-06-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation of a RISC Processor with a Complex Instruction Accelerator 
Sub Title (in English) Return to a CISC 
Keyword(1) Hardware Accelerator  
Keyword(2) Processor architecture  
Keyword(3) Co-processor  
Keyword(4) FPGA  
1st Author's Name Ryota Suzuki  
1st Author's Affiliation Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Tech.)
2nd Author's Name Takefumi Miyoshi  
2nd Author's Affiliation e-trees.Japan, Inc (e-trees)
3rd Author's Name Hironori Nakajo  
3rd Author's Affiliation Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Tech.)
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Date Time 2014-06-12 15:35:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-RECONF2014-13 
Volume (vol) IEICE-114 
Number (no) no.75 
Page pp.67-72 
#Pages IEICE-6 
Date of Issue IEICE-RECONF-2014-06-04 

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