| IEICE Technical Committee Submission System Conference Paper's Information |
Online Proceedings [Sign in] Tech. Rep. Archives |
| Go Top Page | Go Previous | [Japanese] / [English] |
| Paper Abstract and Keywords | ||
| Presentation | 2014-05-29 11:05 Proposal of a Synthesis Flow for Asynchronous Circuits with Bundled-Data Implementation from a SystemC Model Taichi Komine, Hiroshi Saito (Univ. of Aizu)  VLD2014-5 |
|
| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper proposes a synthesis flow for asynchronous circuits with bundled-data implementation from a SystemC model to the layout design. In the proposed synthesis flow, we use commercial EDA tools for high-level synthesis, logic synthesis, layout synthesis, and STA. On the other hand, we develop design automation tools for converting RTL model of synchronous circuits to asynchronous one, generating design constraints, verifying timing, and adjusting timing. In a case study, we synthesize SystemC model of Elliptic Wave Filter using the proposed synthesis flow and evaluate circuit area and energy consumption. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Asynchronous circuits with bundled-data implementation / High-level synthesis / Desynchronization / Constraint generation / Timing verification / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 59, VLD2014-5, pp. 21-26, May 2014. | |
| Paper # | VLD2014-5 | |
| Date of Issue | 2014-05-22 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2014-5 |
|
| Conference Information | |
| Committee | VLD IPSJ-SLDM |
| Conference Date | 2014-05-28 - 2014-05-29 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kitakyushu International Conference Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System Design, etc. |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2014-05-VLD-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Proposal of a Synthesis Flow for Asynchronous Circuits with Bundled-Data Implementation from a SystemC Model |
| Sub Title (in English) | |
| Keyword(1) | Asynchronous circuits with bundled-data implementation |
| Keyword(2) | High-level synthesis |
| Keyword(3) | Desynchronization |
| Keyword(4) | Constraint generation |
| Keyword(5) | Timing verification |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Taichi Komine |
| 1st Author's Affiliation | University of Aizu (Univ. of Aizu) |
| 2nd Author's Name | Hiroshi Saito |
| 2nd Author's Affiliation | University of Aizu (Univ. of Aizu) |
| 3rd Author's Name | |
| 3rd Author's Affiliation | () |
| 4th Author's Name | |
| 4th Author's Affiliation | () |
| 5th Author's Name | |
| 5th Author's Affiliation | () |
| 6th Author's Name | |
| 6th Author's Affiliation | () |
| 7th Author's Name | |
| 7th Author's Affiliation | () |
| 8th Author's Name | |
| 8th Author's Affiliation | () |
| 9th Author's Name | |
| 9th Author's Affiliation | () |
| 10th Author's Name | |
| 10th Author's Affiliation | () |
| 11th Author's Name | |
| 11th Author's Affiliation | () |
| 12th Author's Name | |
| 12th Author's Affiliation | () |
| 13th Author's Name | |
| 13th Author's Affiliation | () |
| 14th Author's Name | |
| 14th Author's Affiliation | () |
| 15th Author's Name | |
| 15th Author's Affiliation | () |
| 16th Author's Name | |
| 16th Author's Affiliation | () |
| 17th Author's Name | |
| 17th Author's Affiliation | () |
| 18th Author's Name | |
| 18th Author's Affiliation | () |
| Speaker | Author-1 |
| Date Time | 2014-05-29 11:05:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2014-5 |
| Volume (vol) | vol.114 |
| Number (no) | no.59 |
| Page | pp.21-26 |
| #Pages | 6 |
| Date of Issue | 2014-05-22 (VLD) |
[Return to Top Page]